From nobody Tue Feb 10 06:58:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1559945051; cv=none; d=zoho.com; s=zohoarc; b=WbXZJRhbqdGQAgX8E/WmF3wJKEGCC0LKDHDVe14cCI45kp9sniSsYzttKdObbQe/OUj76fE8lW9M6eK/jzUss/SwZhnWQUEiyW96HjVov8I4dD20A0q/nU0XpwttLgxgcUU4iBXwjbR2GDEeau0BtgDCiaSH8SqnPwwuzc81dlU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559945051; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To:ARC-Authentication-Results; bh=91HKHxmt0tEAuGXI30vJJJQCx9xRRUsFPjT8+ZIRaOw=; b=I7zAdXuFHuMBIggjszqFm/AepKAo/I00VD8WrVGtz0iXkpUtrV7QDGd0Tg7EC77S6P5IaKE2N4PxdloHL8iN9KMgtbG6ZfEUefitM4YumxoJ4GOLlnUk2wpRMxbGIKfLNUive7oB8L4d20L26hiE3kX25uGujavgS0R9ot9NLIY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=fail header.i=@wdc.com; spf=pass (zoho.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1559945051481916.411939121897; Fri, 7 Jun 2019 15:04:11 -0700 (PDT) Received: from localhost ([::1]:53592 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hZMxx-0007Hu-FG for importer@patchew.org; Fri, 07 Jun 2019 18:04:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47640) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hZMrt-000422-HU for qemu-devel@nongnu.org; Fri, 07 Jun 2019 17:57:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hZMrr-0001fO-LR for qemu-devel@nongnu.org; Fri, 07 Jun 2019 17:57:49 -0400 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:8430) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hZMrr-0001Pu-8h; Fri, 07 Jun 2019 17:57:47 -0400 Received: from h199-255-45-15.hgst.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 08 Jun 2019 05:57:38 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 07 Jun 2019 14:34:53 -0700 Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.140]) by uls-op-cesaip02.wdc.com with ESMTP; 07 Jun 2019 14:57:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1559944668; x=1591480668; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Fvl20bL70W6URC8x1oiu+t8B2haDxcStjjs1M9AXrF0=; b=eXRF4pPcBIMG3/H40Z3QrdPk/iGB2lPG8WBW4sWrG0JZJWcUJy8bJI5q WDI3249t0mEf56/oyS1HKAVEjI7VymZIkde4VWgU2zQ8AskPuKcIMGTnh 3jFzBLtrAMLSkTKcVcOq5qKNI5KXeS88FRBzcu4VWDjt2kABGKHKcTw6L VC+UNYRzzHMeEwQr4/BlD4Bowdm1EUEe3w3H8eeAWJipGd8sTTL/KdF6O Ka7NFhLMJQ0PgtKHChSj0qv4iYphUK41hHaJQriL2SrqiQQMuhviUQQZC 856mJCsaGq7NFJ7GV73ARFIFFjN7M6VOyWjreBRN0L5iFAdRIQFaJv154 w==; X-IronPort-AV: E=Sophos;i="5.63,564,1557158400"; d="scan'208";a="115014077" IronPort-SDR: wyG/T8MH6DVqIFaop1zfLNxRzNrhBcHW+7ZpaA2pbqywYaMY9NUwFcxJwCgStlpCw8rA9T3iC3 g3LH+ARpVn2dkRoFL+PtiZbeFz4QhOcOQ5ePhYmrXXPXNtq+7NLNaxzbxk3XoXWg/JXLi3pNMc ZYN9YrXBF18TPMyR073+dnfgeYO1zArHskObZgALEHAjr8gsVABS0Qd1UvaGDoLUhlpvVaLnKi w2+1FbtpHCHcewvExWpWIDDetKUd4NBbn+X0ev9q/+ZZHzVt6HmAdDPJ51Hi7GkFg7DlaVQR5z uwXtqCfsWJDAmmhuq0cUZDCs IronPort-SDR: 9tcQlM9Y2r7jN1rsFOMboBDnQ/pd2MDECyzR0lXILzyG1J+5HkKdoLfjVG7Q+Kfkq09+qSysC0 H/hRKfLZ8hQYF7vXJzS4EipsOXWofpk+imvWu40pM+lkSsBHjyN1s5NwL3dPeJImc0cPzhmfqM gXGJU/eoUU73f3YUjRGOne+5ymK58J8QUkuRsQUEDJETMIYELQOl6wvqibYTu0rsR85iO5j4mC s3W5qzkfAkGNeyvHgLFppkt223q//tOuQBEOSUl4jatStOM/OjuRHH1V5h5kQ6vN3f2wclB6HR yPg= From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 7 Jun 2019 14:55:27 -0700 Message-Id: X-Mailer: git-send-email 2.21.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [PATCH v1 03/27] target/riscv: Add the virtulisation mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu_bits.h | 6 ++++++ target/riscv/cpu_helper.c | 23 +++++++++++++++++++++++ 3 files changed, 33 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3337d1aef3..de4843b879 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -132,6 +132,8 @@ struct CPURISCVState { =20 #ifndef CONFIG_USER_ONLY target_ulong priv; + /* This contains QEMU specific information about the virt state. */ + target_ulong virt; target_ulong resetvec; =20 target_ulong mhartid; @@ -278,6 +280,8 @@ void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); +bool riscv_cpu_virt_enabled(CPURISCVState *env); +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index dc9d53d4be..07c95e8d2c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -417,6 +417,12 @@ #define PRV_H 2 /* Reserved */ #define PRV_M 3 =20 +/* Virtulisation modes */ +#define VIRT_OFF 0 +#define VIRT_ON 1 +#define VIRT_MODE_SHIFT 0 +#define VIRT_MODE_MASK (1 << VIRT_MODE_SHIFT) + /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 #define SATP32_ASID 0x7fc00000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 872835177a..5912ae63b7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,6 +71,29 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) =20 #if !defined(CONFIG_USER_ONLY) =20 +bool riscv_cpu_virt_enabled(CPURISCVState *env) +{ + bool tmp; + + if (!riscv_has_ext(env, RVH)) { + return false; + } + + tmp =3D (env->virt & VIRT_MODE_MASK) >> VIRT_MODE_SHIFT; + + return tmp =3D=3D VIRT_ON; +} + +void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt &=3D ~VIRT_MODE_MASK; + env->virt |=3D enable << VIRT_MODE_SHIFT; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; --=20 2.21.0