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x=1615067054; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=05Q1mBpOGmEOAS6Fful2qHlv72Yzd6EzLEwaVFrElcg=; b=rb3lspD/A5+FH/RZzVfg3hldak8+gpsElC1JGJhJAGqHfp5hAlm/8b+i FBxJSHzSg7s/o4+cvjGOQDFQb5EgQlbByz4E280h4HQQU9HRy4R0x8ON4 3XeKbyrCFZiUeUnMi0hSqklzTnHFTX6fknPZlhQZSXr8HHaSp+eJiPi8G L7bnzyY1tVBkHeZlUbOTcOqWdmotwUnMCX4HfqH9gnypl0K0YsMCgDdQM pAqyn2pibqvxB8LEAAVG81T2JkRnJ8+bNDkZkEPPN51cs0FRY+vZ/4Y/T XnnnorDAJJT0618TTvdWZ1fgufI8mkXgPNLLSbiBabMaty0AJZzLBH8GV Q==; IronPort-SDR: /rCpoR6/JoQeWjZqlxn8h9dkJKsjY/BbjJ0qt9tkEuOycwsom1JFukJsEHNHCxUNRpNGCWMbPv WeVUhZpHV5gtHT3X3cnoL5qcPC51m8NLZLJ/1te+JZuLTwPe6+mA+1cgphAknkO2/RfXqkHZih XX6/Ip/vvxLDYLs864gtUZsO3CjtL0Bdk9Hub4uyIIQXmg02iuS7VKaYL8Ngs69WAxwBB9/wYV JN7SeWWt4MAWWNM5lFHFDbpWbdr2DdOO4dYFM5mox2K1oEX9WGXWqvbKdqU7Cqu1fCg71MdQ1U gP0= X-IronPort-AV: E=Sophos;i="5.70,523,1574092800"; d="scan'208";a="233784271" IronPort-SDR: EnvuAOlnYxCmFXTBIro8FdSq6bdSc0IxLNbvXhhcqLOMnhMtEtG3X5kSWInJP4h8iKJJu+puAG aq3qwTaYmRoFmlRSGn2RjFxtHOrYDj8tcWH7DCsRjl88nM0mDIlZbp0wSxPSIOmC1TXBFYBd6+ I8nngBlSMhvUdpNIb+IT2ctuEznxOrg/Lb96vOLIPEtEb2uwd/QyRE2h5oobo+giu/OgdlVpAC GlvS78wI2hVvOjjyvcBbVperYuYqDed1w14tmF9HP/LtRV9QDDFvPhmEN7MkHyAZWbDJ+yCCBV FkvFthrt+szMmziTo+97YHQQ IronPort-SDR: nH/w6hAdohxTcymeNl5wzeCRd8cJDJoh8f1NcjM2LHH3zPPPAejXn7ufbYRA45arRQxlFK3XXm ++ZFfI/0atFMGGHFV4M/pQKiWiCznAAjpQLpOTJz7g2aWZlajbWKxLC4GLBeL57nsNX25zToRO 11P1Vnxh8gS93sNiEShcLwwkdYc6uwgsBm/IrgF3t/7o9JXfClCDz0s6rjANdMq+vTlH3+XzMH rLNLXu873oetn3qK77w0KImt2BpRgK3p2U1K6KBywdBfYMoHetT/E6TAR0xfISW28eJARg97tm eiQ= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 1/3] riscv/sifive_u: Fix up file ordering Date: Fri, 6 Mar 2020 13:36:47 -0800 Message-Id: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 68.232.143.124 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Split the file into clear machine and SoC sections. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/sifive_u.c | 109 ++++++++++++++++++++++---------------------- 1 file changed, 55 insertions(+), 54 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 156a003642..4688837216 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -308,7 +308,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, g_free(nodename); } =20 -static void riscv_sifive_u_init(MachineState *machine) +static void sifive_u_machine_init(MachineState *machine) { const struct MemmapEntry *memmap =3D sifive_u_memmap; SiFiveUState *s =3D RISCV_U_MACHINE(machine); @@ -399,6 +399,60 @@ static void riscv_sifive_u_init(MachineState *machine) &address_space_memory); } =20 +static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + return s->start_in_flash; +} + +static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, E= rror **errp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D value; +} + +static void sifive_u_machine_instance_init(Object *obj) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D false; + object_property_add_bool(obj, "start-in-flash", sifive_u_machine_get_s= tart_in_flash, + sifive_u_machine_set_start_in_flash, NULL); + object_property_set_description(obj, "start-in-flash", + "Set on to tell QEMU's ROM to jump to = " \ + "flash. Otherwise QEMU will jump to DR= AM", + NULL); +} + + +static void sifive_u_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; + mc->init =3D sifive_u_machine_init; + mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; + mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus =3D mc->min_cpus; +} + +static const TypeInfo sifive_u_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("sifive_u"), + .parent =3D TYPE_MACHINE, + .class_init =3D sifive_u_machine_class_init, + .instance_init =3D sifive_u_machine_instance_init, + .instance_size =3D sizeof(SiFiveUState), +}; + +static void sifive_u_machine_init_register_types(void) +{ + type_register_static(&sifive_u_machine_typeinfo); +} + +type_init(sifive_u_machine_init_register_types) + static void riscv_sifive_u_soc_init(Object *obj) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -439,33 +493,6 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } =20 -static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - return s->start_in_flash; -} - -static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **e= rrp) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - s->start_in_flash =3D value; -} - -static void riscv_sifive_u_machine_instance_init(Object *obj) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - s->start_in_flash =3D false; - object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_= flash, - sifive_u_set_start_in_flash, NULL); - object_property_set_description(obj, "start-in-flash", - "Set on to tell QEMU's ROM to jump to = " \ - "flash. Otherwise QEMU will jump to DR= AM", - NULL); -} - static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -603,29 +630,3 @@ static void riscv_sifive_u_soc_register_types(void) } =20 type_init(riscv_sifive_u_soc_register_types) - -static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - - mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; - mc->init =3D riscv_sifive_u_init; - mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; - mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpus =3D mc->min_cpus; -} - -static const TypeInfo riscv_sifive_u_machine_typeinfo =3D { - .name =3D MACHINE_TYPE_NAME("sifive_u"), - .parent =3D TYPE_MACHINE, - .class_init =3D riscv_sifive_u_machine_class_init, - .instance_init =3D riscv_sifive_u_machine_instance_init, - .instance_size =3D sizeof(SiFiveUState), -}; - -static void riscv_sifive_u_machine_init_register_types(void) -{ - type_register_static(&riscv_sifive_u_machine_typeinfo); -} - -type_init(riscv_sifive_u_machine_init_register_types) --=20 2.25.1