From nobody Mon Feb 9 09:23:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1666196072579656.381442108362; Wed, 19 Oct 2022 09:14:32 -0700 (PDT) Received: from localhost ([::1]:50636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1olBiA-0001ll-Cb for importer@patchew.org; Wed, 19 Oct 2022 12:14:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1olBX3-0006FE-1Q; Wed, 19 Oct 2022 12:03:01 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:60149) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1olBX0-0001S0-8d; Wed, 19 Oct 2022 12:03:00 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 6D48975A175; Wed, 19 Oct 2022 18:02:54 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 3712D75A16C; Wed, 19 Oct 2022 18:02:54 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v7 3/8] ppc4xx_sdram: Move ppc4xx_sdram_banks() to ppc4xx_sdram.c MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, philmd@linaro.org, Daniel Henrique Barboza Date: Wed, 19 Oct 2022 18:02:54 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1666196073800100001 Content-Type: text/plain; charset="utf-8" This function is only used by the ppc4xx memory controller models so it can be made static. Signed-off-by: BALATON Zoltan Reviewed-by: Daniel Henrique Barboza --- hw/ppc/ppc4xx_devs.c | 62 ----------------------------------------- hw/ppc/ppc4xx_sdram.c | 61 ++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/ppc4xx.h | 20 ++++++------- 3 files changed, 69 insertions(+), 74 deletions(-) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index f737dbb3d6..c1d111465d 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -23,73 +23,11 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" #include "cpu.h" #include "hw/ppc/ppc4xx.h" #include "hw/qdev-properties.h" #include "qapi/error.h" =20 -/* - * Split RAM between SDRAM banks. - * - * sdram_bank_sizes[] must be in descending order, that is sizes[i] > size= s[i+1] - * and must be 0-terminated. - * - * The 4xx SDRAM controller supports a small number of banks, and each bank - * must be one of a small set of sizes. The number of banks and the suppor= ted - * sizes varies by SoC. - */ -void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, - Ppc4xxSdramBank ram_banks[], - const ram_addr_t sdram_bank_sizes[]) -{ - ram_addr_t size_left =3D memory_region_size(ram); - ram_addr_t base =3D 0; - ram_addr_t bank_size; - int i; - int j; - - for (i =3D 0; i < nr_banks; i++) { - for (j =3D 0; sdram_bank_sizes[j] !=3D 0; j++) { - bank_size =3D sdram_bank_sizes[j]; - if (bank_size <=3D size_left) { - char name[32]; - - ram_banks[i].base =3D base; - ram_banks[i].size =3D bank_size; - base +=3D bank_size; - size_left -=3D bank_size; - snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); - memory_region_init_alias(&ram_banks[i].ram, NULL, name, ra= m, - ram_banks[i].base, ram_banks[i].s= ize); - break; - } - } - if (!size_left) { - /* No need to use the remaining banks. */ - break; - } - } - - if (size_left) { - ram_addr_t used_size =3D memory_region_size(ram) - size_left; - GString *s =3D g_string_new(NULL); - - for (i =3D 0; sdram_bank_sizes[i]; i++) { - g_string_append_printf(s, "%" PRIi64 "%s", - sdram_bank_sizes[i] / MiB, - sdram_bank_sizes[i + 1] ? ", " : ""); - } - error_report("at most %d bank%s of %s MiB each supported", - nr_banks, nr_banks =3D=3D 1 ? "" : "s", s->str); - error_printf("Possible valid RAM size: %" PRIi64 " MiB\n", - used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); - - g_string_free(s, true); - exit(EXIT_FAILURE); - } -} - /*************************************************************************= ****/ /* MAL */ =20 diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index d88363bc3d..62ef7d8f0d 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -43,6 +43,67 @@ /*************************************************************************= ****/ /* Shared functions */ =20 +/* + * Split RAM between SDRAM banks. + * + * sdram_bank_sizes[] must be in descending order, that is sizes[i] > size= s[i+1] + * and must be 0-terminated. + * + * The 4xx SDRAM controller supports a small number of banks, and each bank + * must be one of a small set of sizes. The number of banks and the suppor= ted + * sizes varies by SoC. + */ +static void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, + Ppc4xxSdramBank ram_banks[], + const ram_addr_t sdram_bank_sizes[]) +{ + ram_addr_t size_left =3D memory_region_size(ram); + ram_addr_t base =3D 0; + ram_addr_t bank_size; + int i; + int j; + + for (i =3D 0; i < nr_banks; i++) { + for (j =3D 0; sdram_bank_sizes[j] !=3D 0; j++) { + bank_size =3D sdram_bank_sizes[j]; + if (bank_size <=3D size_left) { + char name[32]; + + ram_banks[i].base =3D base; + ram_banks[i].size =3D bank_size; + base +=3D bank_size; + size_left -=3D bank_size; + snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); + memory_region_init_alias(&ram_banks[i].ram, NULL, name, ra= m, + ram_banks[i].base, ram_banks[i].s= ize); + break; + } + } + if (!size_left) { + /* No need to use the remaining banks. */ + break; + } + } + + if (size_left) { + ram_addr_t used_size =3D memory_region_size(ram) - size_left; + GString *s =3D g_string_new(NULL); + + for (i =3D 0; sdram_bank_sizes[i]; i++) { + g_string_append_printf(s, "%" PRIi64 "%s", + sdram_bank_sizes[i] / MiB, + sdram_bank_sizes[i + 1] ? ", " : ""); + } + error_report("at most %d bank%s of %s MiB each supported", + nr_banks, nr_banks =3D=3D 1 ? "" : "s", s->str); + error_printf("Possible valid RAM size: %" PRIi64 " MiB\n", + used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); + + g_string_free(s, true); + exit(EXIT_FAILURE); + } +} + static void sdram_bank_map(Ppc4xxSdramBank *bank) { memory_region_init(&bank->container, NULL, "sdram-container", bank->si= ze); diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 10c6dd535f..f8c86e09ec 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -29,18 +29,6 @@ #include "exec/memory.h" #include "hw/sysbus.h" =20 -typedef struct { - MemoryRegion ram; - MemoryRegion container; /* used for clipping */ - hwaddr base; - hwaddr size; - uint32_t bcr; -} Ppc4xxSdramBank; - -void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, - Ppc4xxSdramBank ram_banks[], - const ram_addr_t sdram_bank_sizes[]); - #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" =20 /* @@ -111,6 +99,14 @@ struct Ppc4xxEbcState { }; =20 /* SDRAM DDR controller */ +typedef struct { + MemoryRegion ram; + MemoryRegion container; /* used for clipping */ + hwaddr base; + hwaddr size; + uint32_t bcr; +} Ppc4xxSdramBank; + #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) #define SDR0_DDR0_DDRM_DDR1 0x20000000 #define SDR0_DDR0_DDRM_DDR2 0x40000000 --=20 2.30.4