From nobody Mon Feb 9 14:34:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1660405499428597.5653068270188; Sat, 13 Aug 2022 08:44:59 -0700 (PDT) Received: from localhost ([::1]:50096 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oMtJq-0007C4-Bx for importer@patchew.org; Sat, 13 Aug 2022 11:44:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9q-00005Q-AC; Sat, 13 Aug 2022 11:34:38 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:28287) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oMt9l-0006IT-Gy; Sat, 13 Aug 2022 11:34:37 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 501A1748194; Sat, 13 Aug 2022 17:34:30 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 1E660748190; Sat, 13 Aug 2022 17:34:30 +0200 (CEST) Message-Id: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH 03/22] ppc/ppc405: QOM'ify GPT MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Sat, 13 Aug 2022 17:34:30 +0200 (CEST) X-Spam-Probability: 10% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1660405500902100001 From: C=C3=A9dric Le Goater The GPT controller is currently modeled as a SysBus device with a unique memory region, a couple of IRQs and a timer. Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 22 ++++++++++ hw/ppc/ppc405_uc.c | 99 ++++++++++++++++++++++++--------------------- hw/ppc/trace-events | 1 - 3 files changed, 75 insertions(+), 47 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 2ba829988d..bcf55e4f6b 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,27 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; =20 +/* General purpose timers */ +#define TYPE_PPC405_GPT "ppc405-gpt" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT); +struct Ppc405GptState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + int64_t tb_offset; + uint32_t tb_freq; + QEMUTimer *timer; + qemu_irq irqs[5]; + uint32_t oe; + uint32_t ol; + uint32_t im; + uint32_t is; + uint32_t ie; + uint32_t comp[5]; + uint32_t mask[5]; +}; + #define TYPE_PPC405_CPC "ppc405-cpc" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405CpcState, PPC405_CPC); =20 @@ -114,6 +135,7 @@ struct Ppc405SoCState { PowerPCCPU cpu; DeviceState *uic; Ppc405CpcState cpc; + Ppc405GptState gpt; }; =20 /* PowerPC 405 core */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index ec83c292a5..bf95fabdc0 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -926,34 +926,18 @@ static void ppc405_ocm_init(CPUPPCState *env) =20 /*************************************************************************= ****/ /* General purpose timers */ -typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; -struct ppc4xx_gpt_t { - MemoryRegion iomem; - int64_t tb_offset; - uint32_t tb_freq; - QEMUTimer *timer; - qemu_irq irqs[5]; - uint32_t oe; - uint32_t ol; - uint32_t im; - uint32_t is; - uint32_t ie; - uint32_t comp[5]; - uint32_t mask[5]; -}; - -static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) +static int ppc4xx_gpt_compare(Ppc405GptState *gpt, int n) { /* XXX: TODO */ return 0; } =20 -static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) +static void ppc4xx_gpt_set_output(Ppc405GptState *gpt, int n, int level) { /* XXX: TODO */ } =20 -static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_set_outputs(Ppc405GptState *gpt) { uint32_t mask; int i; @@ -974,7 +958,7 @@ static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) } } =20 -static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_set_irqs(Ppc405GptState *gpt) { uint32_t mask; int i; @@ -989,14 +973,14 @@ static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) } } =20 -static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) +static void ppc4xx_gpt_compute_timer(Ppc405GptState *gpt) { /* XXX: TODO */ } =20 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) { - ppc4xx_gpt_t *gpt =3D opaque; + Ppc405GptState *gpt =3D opaque; uint32_t ret; int idx; =20 @@ -1050,7 +1034,7 @@ static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr = addr, unsigned size) static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ppc4xx_gpt_t *gpt =3D opaque; + Ppc405GptState *gpt =3D opaque; int idx; =20 trace_ppc4xx_gpt_write(addr, size, value); @@ -1114,22 +1098,20 @@ static const MemoryRegionOps gpt_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static void ppc4xx_gpt_cb (void *opaque) +static void ppc4xx_gpt_cb(void *opaque) { - ppc4xx_gpt_t *gpt; + Ppc405GptState *gpt =3D opaque; =20 - gpt =3D opaque; ppc4xx_gpt_set_irqs(gpt); ppc4xx_gpt_set_outputs(gpt); ppc4xx_gpt_compute_timer(gpt); } =20 -static void ppc4xx_gpt_reset (void *opaque) +static void ppc405_gpt_reset(DeviceState *dev) { - ppc4xx_gpt_t *gpt; + Ppc405GptState *gpt =3D PPC405_GPT(dev); int i; =20 - gpt =3D opaque; timer_del(gpt->timer); gpt->oe =3D 0x00000000; gpt->ol =3D 0x00000000; @@ -1142,21 +1124,34 @@ static void ppc4xx_gpt_reset (void *opaque) } } =20 -static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) +static void ppc405_gpt_realize(DeviceState *dev, Error **errp) { - ppc4xx_gpt_t *gpt; + Ppc405GptState *s =3D PPC405_GPT(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); int i; =20 - trace_ppc4xx_gpt_init(base); + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, s); + memory_region_init_io(&s->iomem, OBJECT(s), &gpt_ops, s, "gpt", 0xd4); + sysbus_init_mmio(sbd, &s->iomem); =20 - gpt =3D g_new0(ppc4xx_gpt_t, 1); - for (i =3D 0; i < 5; i++) { - gpt->irqs[i] =3D irqs[i]; + for (i =3D 0; i < ARRAY_SIZE(s->irqs); i++) { + sysbus_init_irq(sbd, &s->irqs[i]); } - gpt->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); - memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); - memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); - qemu_register_reset(ppc4xx_gpt_reset, gpt); +} + +static void ppc405_gpt_finalize(Object *obj) +{ + timer_del(PPC405_GPT(obj)->timer); +} + +static void ppc405_gpt_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D ppc405_gpt_realize; + dc->reset =3D ppc405_gpt_reset; + /* Reason: only works as function of a ppc4xx SoC */ + dc->user_creatable =3D false; } =20 /*************************************************************************= ****/ @@ -1420,6 +1415,8 @@ static void ppc405_soc_instance_init(Object *obj) =20 object_initialize_child(obj, "cpc", &s->cpc, TYPE_PPC405_CPC); object_property_add_alias(obj, "sys-clk", OBJECT(&s->cpc), "sys-clk"); + + object_initialize_child(obj, "gpt", &s->gpt, TYPE_PPC405_GPT); } =20 static void ppc405_reset(void *opaque) @@ -1430,8 +1427,10 @@ static void ppc405_reset(void *opaque) static void ppc405_soc_realize(DeviceState *dev, Error **errp) { Ppc405SoCState *s =3D PPC405_SOC(dev); - qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; + qemu_irq dma_irqs[4], mal_irqs[4]; CPUPPCState *env; + SysBusDevice *sbd; + int i; =20 /* init CPUs */ if (!qdev_realize(DEVICE(&s->cpu), NULL, errp)) { @@ -1517,12 +1516,14 @@ static void ppc405_soc_realize(DeviceState *dev, Er= ror **errp) ppc405_ocm_init(env); =20 /* GPT */ - gpt_irqs[0] =3D qdev_get_gpio_in(s->uic, 19); - gpt_irqs[1] =3D qdev_get_gpio_in(s->uic, 20); - gpt_irqs[2] =3D qdev_get_gpio_in(s->uic, 21); - gpt_irqs[3] =3D qdev_get_gpio_in(s->uic, 22); - gpt_irqs[4] =3D qdev_get_gpio_in(s->uic, 23); - ppc4xx_gpt_init(0xef600000, gpt_irqs); + sbd =3D SYS_BUS_DEVICE(&s->gpt); + if (!sysbus_realize(sbd, errp)) { + return; + } + sysbus_mmio_map(sbd, 0, 0xef600000); + for (i =3D 0; i < ARRAY_SIZE(s->gpt.irqs); i++) { + sysbus_connect_irq(sbd, i, qdev_get_gpio_in(s->uic, 19 + i)); + } =20 /* MAL */ mal_irqs[0] =3D qdev_get_gpio_in(s->uic, 11); @@ -1555,6 +1556,12 @@ static void ppc405_soc_class_init(ObjectClass *oc, v= oid *data) =20 static const TypeInfo ppc405_types[] =3D { { + .name =3D TYPE_PPC405_GPT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Ppc405GptState), + .instance_finalize =3D ppc405_gpt_finalize, + .class_init =3D ppc405_gpt_class_init, + }, { .name =3D TYPE_PPC405_CPC, .parent =3D TYPE_PPC4xx_DCR_DEVICE, .instance_size =3D sizeof(Ppc405CpcState), diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 5c0a215cad..adb4500888 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -162,7 +162,6 @@ ocm_unmap(const char* prefix, uint32_t isarc) "OCM unma= p %s 0x%08" PRIx32 =20 ppc4xx_gpt_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d" ppc4xx_gpt_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PR= Ix64 " size %d =3D 0x%" PRIx64 -ppc4xx_gpt_init(uint64_t addr) "offet 0x%" PRIx64 =20 ppc405ep_clocks_compute(const char *param, uint32_t param2, uint32_t val) = "%s 0x%1" PRIx32 " %d" ppc405ep_clocks_setup(const char *trace) "%s" --=20 2.30.4