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a=rsa-sha256; c=relaxed/relaxed; d=ecloud.org; s=dreamhost; t=1785404511; bh=WViL1EMWLU+Kff/et70zoHllixe0Hpz9AyIvFg/wGhs=; h=Date:From:To:Subject:Content-Type; b=czD9Ze9XIIRR3fK4B+BTDaR9hijvqhUl1KeETOZPy6B+Vg0ud548IBH5TSuVrfxm+ Y7ArCyn7s1da33uURZ2QeEEZHAJc+du1HCOHiOG+kSh7Ca8dSyLTcg3d9JWqTq703o cI1/TLKJ4AlCiWVgoeVW7PykS2+Dz/4nWn0OhOFHTwdxvrpzZpdkWZgzgegf6th3Kj ZrnF+Z/1ddZJJrscgb3vowonS4BpUpAEDFt1A/XCoiTx9LWgpvUjM2qGSdesdsrUju HI+JC1vYRC+R6mh9YTfmkN1iD2OGXZp3ZUG57lmD8cWdpj2wBj+JlWGSnpW7B2lqWm UEAOCAhHLTdiw== Date: Thu, 30 Jul 2026 11:41:47 +0200 From: Shawn Rutledge To: qemu-devel@nongnu.org Subject: [PATCH] hw/riscv/virt: add dram-base machine property Message-ID: MIME-Version: 1.0 Content-Disposition: inline Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=23.83.209.48; envelope-from=lists@ecloud.org; helo=dog.birch.relay.mailchannels.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.10.1.5.2/285.392.77 X-ZohoMail-DKIM: pass (identity @ecloud.org) X-ZM-MESSAGEID: 1785404565406158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The 'virt' RISC-V machine hardcodes its DRAM base to 0x80000000. Real-world RISC-V SoCs put DRAM elsewhere (SpacemiT K1 at 0x40000000, SpacemiT K3 at 0x100000000, etc.), which forces ports that target those boards to build separate kernels for QEMU testing. Add a 'dram-base' string property that lets users move VIRT_DRAM up without rebuilding QEMU. Values must be 2 MiB-aligned and at or above the default 0x80000000 to avoid colliding with statically- placed MMIO regions (PCIE_MMIO ends at 0x80000000). Lower bases would also require moving PCIE_MMIO/IMSIC/etc. and are rejected with an explicit error pointing at the cause. Example: qemu-system-riscv64 -machine virt,dram-base=3D0x100000000 -m 6G ... runs OpenSBI at firmware base 0x100000000, matching K3 memory layout. Signed-off-by: Shawn Rutledge --- hw/riscv/virt.c | 59 ++++++++++++++++++++++++++++++++++++++++- include/hw/riscv/virt.h | 2 ++ 2 files changed, 60 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 51bac47a91..6ccc98842f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -20,6 +20,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/cutils.h" #include "qemu/error-report.h" #include "qemu/guest-random.h" #include "qapi/error.h" @@ -1307,7 +1308,13 @@ static void virt_machine_init(MachineState *machine) int i, base_hartid, hart_count; int socket_count =3D riscv_socket_count(machine); =20 - s->memmap =3D virt_memmap; + if (s->dram_base) { + s->memmap_storage =3D g_memdup2(virt_memmap, sizeof(virt_memmap)); + s->memmap_storage[VIRT_DRAM].base =3D s->dram_base; + s->memmap =3D s->memmap_storage; + } else { + s->memmap =3D virt_memmap; + } =20 /* Check socket count limit */ if (VIRT_SOCKETS_MAX < socket_count) { @@ -1545,6 +1552,7 @@ static void virt_machine_instance_finalize(Object *ob= j) } g_free(s->oem_id); g_free(s->oem_table_id); + g_free(s->memmap_storage); } =20 static void virt_machine_instance_init(Object *obj) @@ -1616,6 +1624,46 @@ static void virt_set_aia(Object *obj, const char *va= l, Error **errp) } } =20 +static char *virt_get_dram_base(Object *obj, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + uint64_t val =3D s->dram_base ? s->dram_base : virt_memmap[VIRT_DRAM].= base; + + return g_strdup_printf("0x%" PRIx64, val); +} + +static void virt_set_dram_base(Object *obj, const char *val, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + const char *endptr; + uint64_t base; + + if (qemu_strtou64(val, &endptr, 0, &base) < 0 || *endptr !=3D '\0') { + error_setg(errp, "Invalid dram-base value '%s'", val); + return; + } + /* + * DRAM must clear all statically-placed MMIO regions in virt_memmap[] + * (PCIE_MMIO ends at 0x80000000) and be 2 MiB-aligned so a standard + * OpenSBI + kernel layout (firmware at base, kernel at base+0x200000) + * fits. Values below the default base would collide with on-board + * MMIO and are rejected. + */ + if (base < virt_memmap[VIRT_DRAM].base) { + error_setg(errp, + "dram-base 0x%" PRIx64 " is below default 0x%" PRIx64 + "; would collide with static MMIO regions", + base, (uint64_t)virt_memmap[VIRT_DRAM].base); + return; + } + if (base & (2 * MiB - 1)) { + error_setg(errp, "dram-base 0x%" PRIx64 " must be 2 MiB-aligned", + base); + return; + } + s->dram_base =3D base; +} + static bool virt_get_aclint(Object *obj, Error **errp) { RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); @@ -1744,6 +1792,15 @@ static void virt_machine_class_init(ObjectClass *oc,= const void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); #endif =20 + object_class_property_add_str(oc, "dram-base", virt_get_dram_base, + virt_set_dram_base); + object_class_property_set_description(oc, "dram-base", + "Base physical address of DRAM " + "(default 0x80000000). Must be " + "2 MiB-aligned and at or above " + "the default to avoid colliding " + "with statically-placed MMIO."); + object_class_property_add_bool(oc, "aclint", virt_get_aclint, virt_set_aclint); object_class_property_set_description(oc, "aclint", diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 36a2def410..be8a4ac049 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -61,6 +61,8 @@ struct RISCVVirtState { char *oem_table_id; OnOffAuto acpi; const MemMapEntry *memmap; + MemMapEntry *memmap_storage; /* g_malloc'd copy when dram-base overrid= e is set */ + uint64_t dram_base; /* 0 =3D use compiled-in default (0x80000= 000) */ struct GPEXHost *gpex_host; OnOffAuto iommu_sys; uint16_t pci_iommu_bdf; --=20 2.55.0