From nobody Mon Feb 9 16:19:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1591635980; cv=none; d=zohomail.com; s=zohoarc; b=GBWZydhPTpHbgEneG4uyOA3PzY6F4DBgSLg3F9W//juFZw49bT3h7VUgX+SG68FW3hKsht2xTP8XBKPx0nGt0OVlyJ+8Txnu5uItM3mW5KUQP0+iVWbSjVQ/on9NmryNCP8C4JP/+4C/3ojHG1tlpIdyxa7eQ3r4CdIMMwJvp4c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591635980; h=Content-Type:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FbiLF2h83o9p0roItfL5xP4l9qRBiUvTXoytfGYF4Rs=; b=B4OyyiO6ePdH5LRG3xapc4tt6/BQRmGM4IvMdOF1wkzObnMv3I0VfbjAXJbGz8u+iUS8Ogvi6dEuKI7MF8zIjEZLPjV1k6/LqW2Pi1WA2BVEtl0+5nFQ9P8/7R1iNT4xplKgHVvYqXHZjZq9mw1nx3fyLbL2pLNY5Vue90smU2w= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591635980066893.3964245184414; Mon, 8 Jun 2020 10:06:20 -0700 (PDT) Received: from localhost ([::1]:37530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jiLE2-0007Aw-6k for importer@patchew.org; Mon, 08 Jun 2020 13:06:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jiL6W-00077p-C6 for qemu-devel@nongnu.org; Mon, 08 Jun 2020 12:58:32 -0400 Received: from esa1.mentor.iphmx.com ([68.232.129.153]:48779) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jiL6U-0001dy-Oj for qemu-devel@nongnu.org; Mon, 08 Jun 2020 12:58:32 -0400 Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa1.mentor.iphmx.com with ESMTP; 08 Jun 2020 08:58:29 -0800 IronPort-SDR: JRVnId0x6zgtSZmxeTfmum1hEz6nDKfzoyjXqMxExNHwgG4Oyg9x5sPUECSAYK6DOYCbtr2Kwn f8TRHgsy5JmTf1xEMES6yG/GpWku+OCq1p+Ki3GFOD/gC9lxwR5dEJQKgdHJ1kM/xY4zSSuKdD UJgMIWTA3og1iX0GuRULI2psBkURfECljL+T4yhnPNBwEkHG7gtcWk2p47dilRyIuxmb1R8Yjo OFOZcvPDKiAhGHx4vUsa3+WKz/fkyxQNrQBczo9/fgpd58TDS4O6GLkBJr4/Oe9YdGbo6nynY3 r3s= X-IronPort-AV: E=Sophos;i="5.73,487,1583222400"; d="scan'208";a="51690378" IronPort-SDR: Q2sJPuVBdSjIhnG12ydreMFqNJUZUnfWr0u4XzRXnsLZaBJbu+ZQQ2JK1jMx2Bl4q8zmfJl2GV XiwB73losVr5kOQocHu7N7zYxy7qlbrzezjpCJx6Z+FMMz/otUSZPVm2jqoRhcJG8DSz1z5WG1 +AwJ7RszjnarGrBsQYjoSJWiWCpslpR55gbRNw8uAiulRyHf8kYcfjXjXZeHMzsd7Qe8tTPD4T Xg7FHqa7N5RS5o1qAcFpClGxXhAckTlQiFNQ+OzHe8wlK9YFhJeWc3Vf49L8qGuVGZ244WLTm5 1Xw= Date: Mon, 8 Jun 2020 16:58:23 +0000 From: Joseph Myers X-X-Sender: jsm28@digraph.polyomino.org.uk To: , , , , , , , Subject: [PATCH v2 6/6] target/i386: reimplement fprem, fprem1 using floatx80 operations In-Reply-To: Message-ID: References: User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-04.mgc.mentorg.com (139.181.222.4) To svr-ies-mbx-02.mgc.mentorg.com (139.181.222.2) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.129.153; envelope-from=joseph_myers@mentor.com; helo=esa1.mentor.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/08 12:51:54 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -39 X-Spam_score: -4.0 X-Spam_bar: ---- X-Spam_report: (-4.0 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The x87 fprem and fprem1 emulation is currently based around conversion to double, which is inherently unsuitable for a good emulation of any floatx80 operation. Reimplement using the soft-float floatx80 remainder operations. Signed-off-by: Joseph Myers Reviewed-by: Richard Henderson --- target/i386/fpu_helper.c | 156 ++++++++++++--------------------------- 1 file changed, 48 insertions(+), 108 deletions(-) diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c index 8ef5b463ea..0e531e3821 100644 --- a/target/i386/fpu_helper.c +++ b/target/i386/fpu_helper.c @@ -934,124 +934,64 @@ void helper_fxtract(CPUX86State *env) merge_exception_flags(env, old_flags); } =20 -void helper_fprem1(CPUX86State *env) +static void helper_fprem_common(CPUX86State *env, bool mod) { - double st0, st1, dblq, fpsrcop, fptemp; - CPU_LDoubleU fpsrcop1, fptemp1; - int expdif; - signed long long int q; - - st0 =3D floatx80_to_double(env, ST0); - st1 =3D floatx80_to_double(env, ST1); - - if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 =3D=3D 0.0)) { - ST0 =3D double_to_floatx80(env, 0.0 / 0.0); /* NaN */ - env->fpus &=3D ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ - return; - } - - fpsrcop =3D st0; - fptemp =3D st1; - fpsrcop1.d =3D ST0; - fptemp1.d =3D ST1; - expdif =3D EXPD(fpsrcop1) - EXPD(fptemp1); - - if (expdif < 0) { - /* optimisation? taken from the AMD docs */ - env->fpus &=3D ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ - /* ST0 is unchanged */ - return; - } + uint8_t old_flags =3D save_exception_flags(env); + uint64_t quotient; + CPU_LDoubleU temp0, temp1; + int exp0, exp1, expdiff; =20 - if (expdif < 53) { - dblq =3D fpsrcop / fptemp; - /* round dblq towards nearest integer */ - dblq =3D rint(dblq); - st0 =3D fpsrcop - fptemp * dblq; + temp0.d =3D ST0; + temp1.d =3D ST1; + exp0 =3D EXPD(temp0); + exp1 =3D EXPD(temp1); =20 - /* convert dblq to q by truncating towards zero */ - if (dblq < 0.0) { - q =3D (signed long long int)(-dblq); + env->fpus &=3D ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ + if (floatx80_is_zero(ST0) || floatx80_is_zero(ST1) || + exp0 =3D=3D 0x7fff || exp1 =3D=3D 0x7fff || + floatx80_invalid_encoding(ST0) || floatx80_invalid_encoding(ST1)) { + ST0 =3D floatx80_modrem(ST0, ST1, mod, "ient, &env->fp_status); + } else { + if (exp0 =3D=3D 0) { + exp0 =3D 1 - clz64(temp0.l.lower); + } + if (exp1 =3D=3D 0) { + exp1 =3D 1 - clz64(temp1.l.lower); + } + expdiff =3D exp0 - exp1; + if (expdiff < 64) { + ST0 =3D floatx80_modrem(ST0, ST1, mod, "ient, &env->fp_sta= tus); + env->fpus |=3D (quotient & 0x4) << (8 - 2); /* (C0) <-- q2 */ + env->fpus |=3D (quotient & 0x2) << (14 - 1); /* (C3) <-- q1 */ + env->fpus |=3D (quotient & 0x1) << (9 - 0); /* (C1) <-- q0 */ } else { - q =3D (signed long long int)dblq; + /* + * Partial remainder. This choice of how many bits to + * process at once is specified in AMD instruction set + * manuals, and empirically is followed by Intel + * processors as well; it ensures that the final remainder + * operation in a loop does produce the correct low three + * bits of the quotient. AMD manuals specify that the + * flags other than C2 are cleared, and empirically Intel + * processors clear them as well. + */ + int n =3D 32 + (expdiff % 32); + temp1.d =3D floatx80_scalbn(temp1.d, expdiff - n, &env->fp_sta= tus); + ST0 =3D floatx80_mod(ST0, temp1.d, &env->fp_status); + env->fpus |=3D 0x400; /* C2 <-- 1 */ } - - env->fpus &=3D ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ - /* (C0,C3,C1) <-- (q2,q1,q0) */ - env->fpus |=3D (q & 0x4) << (8 - 2); /* (C0) <-- q2 */ - env->fpus |=3D (q & 0x2) << (14 - 1); /* (C3) <-- q1 */ - env->fpus |=3D (q & 0x1) << (9 - 0); /* (C1) <-- q0 */ - } else { - env->fpus |=3D 0x400; /* C2 <-- 1 */ - fptemp =3D pow(2.0, expdif - 50); - fpsrcop =3D (st0 / st1) / fptemp; - /* fpsrcop =3D integer obtained by chopping */ - fpsrcop =3D (fpsrcop < 0.0) ? - -(floor(fabs(fpsrcop))) : floor(fpsrcop); - st0 -=3D (st1 * fpsrcop * fptemp); } - ST0 =3D double_to_floatx80(env, st0); + merge_exception_flags(env, old_flags); } =20 -void helper_fprem(CPUX86State *env) +void helper_fprem1(CPUX86State *env) { - double st0, st1, dblq, fpsrcop, fptemp; - CPU_LDoubleU fpsrcop1, fptemp1; - int expdif; - signed long long int q; - - st0 =3D floatx80_to_double(env, ST0); - st1 =3D floatx80_to_double(env, ST1); - - if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 =3D=3D 0.0)) { - ST0 =3D double_to_floatx80(env, 0.0 / 0.0); /* NaN */ - env->fpus &=3D ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ - return; - } - - fpsrcop =3D st0; - fptemp =3D st1; - fpsrcop1.d =3D ST0; - fptemp1.d =3D ST1; - expdif =3D EXPD(fpsrcop1) - EXPD(fptemp1); - - if (expdif < 0) { - /* optimisation? taken from the AMD docs */ - env->fpus &=3D ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ - /* ST0 is unchanged */ - return; - } - - if (expdif < 53) { - dblq =3D fpsrcop / fptemp; /* ST0 / ST1 */ - /* round dblq towards zero */ - dblq =3D (dblq < 0.0) ? ceil(dblq) : floor(dblq); - st0 =3D fpsrcop - fptemp * dblq; /* fpsrcop is ST0 */ - - /* convert dblq to q by truncating towards zero */ - if (dblq < 0.0) { - q =3D (signed long long int)(-dblq); - } else { - q =3D (signed long long int)dblq; - } - - env->fpus &=3D ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ - /* (C0,C3,C1) <-- (q2,q1,q0) */ - env->fpus |=3D (q & 0x4) << (8 - 2); /* (C0) <-- q2 */ - env->fpus |=3D (q & 0x2) << (14 - 1); /* (C3) <-- q1 */ - env->fpus |=3D (q & 0x1) << (9 - 0); /* (C1) <-- q0 */ - } else { - int N =3D 32 + (expdif % 32); /* as per AMD docs */ + helper_fprem_common(env, false); +} =20 - env->fpus |=3D 0x400; /* C2 <-- 1 */ - fptemp =3D pow(2.0, (double)(expdif - N)); - fpsrcop =3D (st0 / st1) / fptemp; - /* fpsrcop =3D integer obtained by chopping */ - fpsrcop =3D (fpsrcop < 0.0) ? - -(floor(fabs(fpsrcop))) : floor(fpsrcop); - st0 -=3D (st1 * fpsrcop * fptemp); - } - ST0 =3D double_to_floatx80(env, st0); +void helper_fprem(CPUX86State *env) +{ + helper_fprem_common(env, true); } =20 void helper_fyl2xp1(CPUX86State *env) --=20 2.17.1 --=20 Joseph S. Myers joseph@codesourcery.com