From nobody Thu May 2 14:47:14 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1510006652104781.7208037843257; Mon, 6 Nov 2017 14:17:32 -0800 (PST) Received: from localhost ([::1]:50492 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eBphm-0004eR-82 for importer@patchew.org; Mon, 06 Nov 2017 17:17:18 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58847) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eBpgg-0003vl-Ez for qemu-devel@nongnu.org; Mon, 06 Nov 2017 17:16:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eBpgf-0001NX-Gl for qemu-devel@nongnu.org; Mon, 06 Nov 2017 17:16:10 -0500 Received: from mail.kernel.org ([198.145.29.99]:36110) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1eBpga-0001La-UU; Mon, 06 Nov 2017 17:16:05 -0500 Received: from [10.149.184.130] (162-198-228-33.lightspeed.wlfrct.sbcglobal.net [162.198.228.33]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id ADC8A21870; Mon, 6 Nov 2017 22:16:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org ADC8A21870 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=sstabellini@kernel.org Date: Mon, 6 Nov 2017 14:16:02 -0800 (PST) From: Stefano Stabellini X-X-Sender: sstabellini@sstabellini-ThinkPad-X260 To: peter.maydell@linaro.org Message-ID: User-Agent: Alpine 2.10 (DEB 1266 2009-07-14) MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 198.145.29.99 Subject: [Qemu-devel] [PATCH v2] aarch64: advertise the GIC system register interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: julien.grall@arm.com, sstabellini@kernel.org, qemu-devel@nongnu.org, qemu-arm@nongnu.org, xen-devel@lists.xen.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: TEXT/PLAIN; charset="utf-8" When QEMU emulates a GICv3, it needs to advertise the presence of the system register interface, which is done via id_aa64pfr0. To do that, and at the same time to avoid advertising the presence of the system register interface when it is actually not available, set a boolean property in machvirt_init. Check on the boolean property from register_cp_regs_for_features and set id_aa64pfr0 accordingly. Signed-off-by: Stefano Stabellini diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9e18b41..369d36b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1401,6 +1401,9 @@ static void machvirt_init(MachineState *machine) object_property_set_link(cpuobj, OBJECT(secure_sysmem), "secure-memory", &error_abort); } + if (vms->gic_version =3D=3D 3) { + object_property_set_bool(cpuobj, true, "gicv3-sysregs", NULL); + } =20 object_property_set_bool(cpuobj, true, "realized", NULL); object_unref(cpuobj); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 88578f3..259cad1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1690,6 +1690,7 @@ static Property arm_cpu_properties[] =3D { DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, ARM64_AFFINITY_INVALID), DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), + DEFINE_PROP_BOOL("gicv3-sysregs", ARMCPU, gicv3_sysregs, false), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 89d49cd..0015b37 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -657,6 +657,9 @@ struct ARMCPU { /* Should CPU start in PSCI powered-off state? */ bool start_powered_off; =20 + /* GICv3 sysregs present */ + bool gicv3_sysregs; + /* Current power state, access guarded by BQL */ ARMPSCIState power_state; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 37af750..6f21900 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4687,7 +4687,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "ID_AA64PFR0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->id_aa64pfr0 }, + .resetvalue =3D cpu->gicv3_sysregs ? (cpu->id_aa64pfr0|0x010= 00000) : + cpu->id_aa64pfr0 }, { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST,