From nobody Mon Feb 9 15:29:47 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1769366148286433.5112904187537; Sun, 25 Jan 2026 10:35:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vk4wF-0006hr-Jv; Sun, 25 Jan 2026 13:34:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vk4wD-0006f8-L1 for qemu-devel@nongnu.org; Sun, 25 Jan 2026 13:34:17 -0500 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vk4wA-0002nG-GX for qemu-devel@nongnu.org; Sun, 25 Jan 2026 13:34:17 -0500 Received: from localhost (localhost [127.0.0.1]) by zero.eik.bme.hu (Postfix) with ESMTP id 755FA5974FE; Sun, 25 Jan 2026 19:34:10 +0100 (CET) Received: from zero.eik.bme.hu ([127.0.0.1]) by localhost (zero.eik.bme.hu [127.0.0.1]) (amavis, port 10028) with ESMTP id v_y9rsM8YZvB; Sun, 25 Jan 2026 19:34:08 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 03ED05974CF; Sun, 25 Jan 2026 18:51:04 +0100 (CET) X-Virus-Scanned: amavis at eik.bme.hu Message-ID: In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v2 08/10] hw/ide/sii3112: Use memory_region_new to avoid leaking regions MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org Cc: Peter Xu , Akihiko Odaki , Paolo Bonzini , Michael S. Tsirkin , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sun, 25 Jan 2026 18:51:04 +0100 (CET) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1769366153133154100 Content-Type: text/plain; charset="utf-8" Memory regions created with memory_region_init are not freed with their owner. Use memory_region_new instead to let QOM manage the lifetime of the memory regions. Signed-off-by: BALATON Zoltan --- hw/ide/sii3112.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 9b28c691fd..d2dcfc3830 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -31,7 +31,7 @@ typedef struct SiI3112Regs { =20 struct SiI3112PCIState { PCIIDEState i; - MemoryRegion mmio; + SiI3112Regs regs[2]; }; =20 @@ -249,39 +249,33 @@ static void sii3112_reset(DeviceState *dev) =20 static void sii3112_pci_realize(PCIDevice *dev, Error **errp) { - SiI3112PCIState *d =3D SII3112_PCI(dev); PCIIDEState *s =3D PCI_IDE(dev); DeviceState *ds =3D DEVICE(dev); - MemoryRegion *mr; - int i; + Object *o =3D OBJECT(dev); + MemoryRegion *mmio, *mr; =20 pci_config_set_interrupt_pin(dev->config, 1); pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8); =20 /* BAR5 is in PCI memory space */ - memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d, - "sii3112.bar5", 0x200); - pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio); + mmio =3D memory_region_new_io(o, &sii3112_reg_ops, SII3112_PCI(dev), + "sii3112.bar5", 0x200); + pci_register_bar(dev, 5, PCI_BASE_ADDRESS_SPACE_MEMORY, mmio); =20 /* BAR0-BAR4 are PCI I/O space aliases into BAR5 */ - mr =3D g_new(MemoryRegion, 1); - memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80= , 8); + mr =3D memory_region_new_alias(o, "sii3112.bar0", mmio, 0x80, 8); pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr); - mr =3D g_new(MemoryRegion, 1); - memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88= , 4); + mr =3D memory_region_new_alias(o, "sii3112.bar1", mmio, 0x88, 4); pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr); - mr =3D g_new(MemoryRegion, 1); - memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0= , 8); + mr =3D memory_region_new_alias(o, "sii3112.bar2", mmio, 0xc0, 8); pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, mr); - mr =3D g_new(MemoryRegion, 1); - memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8= , 4); + mr =3D memory_region_new_alias(o, "sii3112.bar3", mmio, 0xc8, 4); pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, mr); - mr =3D g_new(MemoryRegion, 1); - memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 1= 6); + mr =3D memory_region_new_alias(o, "sii3112.bar4", mmio, 0, 16); pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr); =20 qdev_init_gpio_in(ds, sii3112_set_irq, 2); - for (i =3D 0; i < 2; i++) { + for (int i =3D 0; i < 2; i++) { ide_bus_init(&s->bus[i], sizeof(s->bus[i]), ds, i, 1); ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i)); =20 --=20 2.41.3