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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcel Apfelbaum Subject: [PULL 12/31] hw/i386/amd_iommu: Move capab_offset from AMDVIState to AMDVIPCIState Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.171, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1682409041879100013 From: Philippe Mathieu-Daud=C3=A9 The 'PCI capability offset' is a *PCI* notion. Since AMDVIPCIState inherits PCIDevice and hold PCI-related fields, move capab_offset from AMDVIState to AMDVIPCIState. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230313153031.86107-5-philmd@linaro.org> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/i386/amd_iommu.h | 2 +- hw/i386/acpi-build.c | 2 +- hw/i386/amd_iommu.c | 14 +++++++------- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 5eccaad790..1c0cb54bd4 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -308,6 +308,7 @@ typedef struct AMDVIAddressSpace AMDVIAddressSpace; /* functions to steal PCI config space */ typedef struct AMDVIPCIState { PCIDevice dev; /* The PCI device itself */ + uint32_t capab_offset; /* capability offset pointer */ } AMDVIPCIState; =20 struct AMDVIState { @@ -315,7 +316,6 @@ struct AMDVIState { AMDVIPCIState pci; /* IOMMU PCI device */ =20 uint32_t version; - uint32_t capab_offset; /* capability offset pointer */ =20 uint64_t mmio_addr; =20 diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index a27bc33956..7f211e1f48 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2399,7 +2399,7 @@ build_amd_iommu(GArray *table_data, BIOSLinker *linke= r, const char *oem_id, object_property_get_int(OBJECT(&s->pci), "ad= dr", &error_abort), 2); /* Capability offset */ - build_append_int_noprefix(table_data, s->capab_offset, 2); + build_append_int_noprefix(table_data, s->pci.capab_offset, 2); /* IOMMU base address */ build_append_int_noprefix(table_data, s->mmio.addr, 8); /* PCI Segment Group */ diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 19f57e6318..9f6622e11f 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1516,15 +1516,15 @@ static void amdvi_init(AMDVIState *s) pci_config_set_class(s->pci.dev.config, 0x0806); =20 /* reset AMDVI specific capabilities, all r/o */ - pci_set_long(s->pci.dev.config + s->capab_offset, AMDVI_CAPAB_FEATURES= ); - pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_BAR_LOW, + pci_set_long(s->pci.dev.config + s->pci.capab_offset, AMDVI_CAPAB_FEAT= URES); + pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_BAR= _LOW, AMDVI_BASE_ADDR & ~(0xffff0000)); - pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_BAR_HIG= H, + pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_BAR= _HIGH, (AMDVI_BASE_ADDR & ~(0xffff)) >> 16); - pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_RANGE, + pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_RAN= GE, 0xff000000); - pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_MISC, 0= ); - pci_set_long(s->pci.dev.config + s->capab_offset + AMDVI_CAPAB_MISC, + pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_MIS= C, 0); + pci_set_long(s->pci.dev.config + s->pci.capab_offset + AMDVI_CAPAB_MIS= C, AMDVI_MAX_PH_ADDR | AMDVI_MAX_GVA_ADDR | AMDVI_MAX_VA_ADDR); } =20 @@ -1557,7 +1557,7 @@ static void amdvi_sysbus_realize(DeviceState *dev, Er= ror **errp) if (ret < 0) { return; } - s->capab_offset =3D ret; + s->pci.capab_offset =3D ret; =20 ret =3D pci_add_capability(&s->pci.dev, PCI_CAP_ID_MSI, 0, AMDVI_CAPAB_REG_SIZE, errp); --=20 MST