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x=1607451421; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/3fxKU2515+FuiCpoyXrQI09sK+MUJhblGNAHmPNsJI=; b=ZYfzs+HlrLo/N3xaTGU/+ZW0tDGqukyKadu+NYBzSg9mV3Io7wt4KQjS v++omEXnhuN4zEWePyGkaCZGJeP7B6yAE+c26HNBbY6qo65jtqD9+D927 /9bocACLlYEtfmG0sJ+LTylBdZzWcAwQiyX72k9oVGzPVG0KyHTtGGWOH 4DXdeMudyikSAgu9IEd4vsoUsIPKT2/piLULlF7YDp8LpBrk6XUcIKgQ9 Drjwu7sId2wWvJcgDNCehBhyfgo9iW259JczDlst6TS1JHVnSGk9JKFgI zB6m4Pj6or/RAfJJ7hUOVUiqkqF3obJWnknjeuUfNRvyMJUDA1oVu6czu Q==; IronPort-SDR: woJDB8AOx3ATFXi//Oe8RP/DZluDZDRqtzCMU1DF6Nrw3OPwOPP8LnCNAoZXszCqI2pnpYcmQu OcXsu8NYUP3wGGTjWXVW/kDQgTl3JSibZ42V8Ti7n3UaIh1+zm8USiVYEZiy3LmTulC9ATG7h3 lfinuVMgMBgjDPLhI2NOyRHnvGrs6Cl8jZUpsMr6e8SD6Vx0yDvYaIVAEl8fp4bMciZk0kfxp+ Tvmdql0RQZlBLiyFCN2fJe4l8I3stqXa9YPGhXE3CSujypol+JCLRu0RxPTN9W19ZPUGowaTBZ Dhg= X-IronPort-AV: E=Sophos;i="5.69,296,1571673600"; d="scan'208";a="226411935" IronPort-SDR: dOa4KWmbd+MYltrt0uuC7ctViy/cu/bxwG/3vbe0B6ma3Um8+c9/KM9sB83uNT6Lf8hby5Qgbo DDO+47jsBF6IEd4lv+xHpmjznfreBxtyRDar+IDt4dcr58pWyjA6fYhIoHeP77yHGi8zF9dS2p wLYNHBSlcoSfLjtzH32b0Ls3QxtS+waj9DgQahBBzvqLu3ilqRd1/IcZwMUMMYZTsSveyl8pGN Pq83iFMioHg7pOyyJhGjuLwMOoIl6gh/t22hPz4MYqNRKNkFHsHHDPiN712L8/XAuNkvVuR6Sm eTeWupMThCNo8z30gplAvMoA IronPort-SDR: 43bvn2/1mRF32MpeGjp5uVkRDValEtxZywZBbyiiJXyCRlzFDLM0xeY9Dnp786trlQrfNG/w1g NRMzAKOAMrc/nd8JjiDT23cy2gO60yL0EIb+KuiCUCXb/9YiqfXOOq19lsNYWbaoR7hX3CyYgP eDEx8ldF9aZu4mYfR03ugIwdb/jPaY+LXstoWnwYSdSMp5Q6QY/ZmL/n1f+rk6aPfIAKVKdvUc 5GVFBt17mlWcJhmvKhAlVYuA75Y3L16fdQieZdvxOw4YXo+H3GybcIiD87sOuPirlLTIfZOAvC CFc= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 08/36] target/riscv: Add the force HS exception mode Date: Mon, 9 Dec 2019 10:11:01 -0800 Message-Id: X-Mailer: git-send-email 2.24.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 68.232.143.124 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a FORCE_HS_EXCEP mode to the RISC-V virtulisation status. This bit specifies if an exeption should be taken to HS mode no matter the current delegation status. This is used when an exeption must be taken to HS mode, such as when handling interrupts. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 6 ++++++ target/riscv/cpu_helper.c | 18 ++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a73292cd20..21ae5a8b19 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -273,6 +273,8 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interru= pt_request); bool riscv_cpu_fp_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 2cdb0de4fe..ad6479796c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -432,6 +432,12 @@ =20 /* Virtulisation Register Fields */ #define VIRT_ONOFF 1 +/* This is used to save state for when we take an exception. If this is set + * that means that we want to force a HS level exception (no matter what t= he + * delegation is set to). This will occur for things such as a second level + * page table fault. + */ +#define FORCE_HS_EXCEP 2 =20 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 046f3549cc..b00f66824a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -100,6 +100,24 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, bo= ol enable) env->virt =3D set_field(env->virt, VIRT_ONOFF, enable); } =20 +bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return false; + } + + return get_field(env->virt, FORCE_HS_EXCEP); +} + +void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt =3D set_field(env->virt, FORCE_HS_EXCEP, enable); +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; --=20 2.24.0