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IronPort-SDR: +FOOvhuv3rJ2gEnE0iFrolOY1mW7jkXjeMqD+49Y/xrQeGoc+ghIWD7u1xNWiWHgQXjEjwfGF2 4H0UoBEDYzh97mrrs8CsMm5WUdfXpi2hXqE3qLObkxWlbbF4BuIrTvi/jARGGugviSAswnRXHw pNCQY1sP3LhsMQWW9LicU9VPCuapAjhjczA/EeaykF9fHA9SSMZxwpV7pA1OdNoEuMvHBFelPH 2Ni3PaXqGbROei8DOtjlNudZ6OYAlafoECFxmise4NJOdy9mZbWQKrfclf3wJQ/DUSHaioMZVM HAM= X-IronPort-AV: E=Sophos;i="5.73,320,1583164800"; d="scan'208";a="137626674" IronPort-SDR: D6GXHfKLaAGKe68MTHqU8wGILDqrRCuuiCr8rI1e98LAR1xoOWEGAiThQDXivKaRE3aj3JRJtb vJZ9gGgRUTTCa/YDbkfDipmt8/DmYyRj8= IronPort-SDR: OS9xMFmjjTKnWZ2rO50f8f+DXqMsu88rHKweqKfW/xjy5uC9tkXzx2tPTKvA45iXHHaU1rPM53 vQoPawoCLe8w== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 05/15] target/riscv: Allow setting a two-stage lookup in the virt status Date: Sun, 26 Apr 2020 09:19:26 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=378a396a1=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/26 12:27:33 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 18 ++++++++++++++++++ 3 files changed, 21 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0e7f5b9c5..e44a7a91e4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -302,6 +302,8 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); +bool riscv_cpu_two_stage_lookup(CPURISCVState *env); +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7f64ee1174..f52711ac32 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -452,6 +452,7 @@ * page table fault. */ #define FORCE_HS_EXCEP 2 +#define HS_TWO_STAGE 4 =20 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 0d4a7b752d..075675c59c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -220,6 +220,24 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, = bool enable) env->virt =3D set_field(env->virt, FORCE_HS_EXCEP, enable); } =20 +bool riscv_cpu_two_stage_lookup(CPURISCVState *env) +{ + if (!riscv_has_ext(env, RVH)) { + return false; + } + + return get_field(env->virt, HS_TWO_STAGE); +} + +void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable) +{ + if (!riscv_has_ext(env, RVH)) { + return; + } + + env->virt =3D set_field(env->virt, HS_TWO_STAGE, enable); +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env =3D &cpu->env; --=20 2.26.2