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Sat, 07 Mar 2026 23:19:16 -0800 (PST) From: Chao Liu To: Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier Cc: tangtao1634@phytium.com.cn, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 08/28] target/riscv: track the exact breakpoint trigger hit Date: Sun, 8 Mar 2026 15:17:11 +0800 Message-ID: X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1344; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772954413204158500 Content-Type: text/plain; charset="utf-8" Store the exact breakpoint trigger index in CPU state when a trigger-backed CPU breakpoint matches so later debug handling can distinguish which slot fired. This simplifies the post-hit path because the expensive matching work has already been done when the trigger was programmed into a QEMU breakpoint object. By the time debug handling runs, the matching breakpoint pointer already identifies the trigger slot, so there is no need to re-decode the execute bits or compare the program counter against tdata2 again. The remaining dynamic checks are the common privilege and textra conditions, which are still revalidated before the trigger action is taken. This avoids collapsing all breakpoint hits into a generic stop and lets ROM-backed Debug Mode entry preserve the original trigger action and metadata. Signed-off-by: Chao Liu --- target/riscv/cpu.h | 1 + target/riscv/debug.c | 81 +++++++++++++++++++++----------------------- 2 files changed, 40 insertions(+), 42 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0bc14f6953..65c7b66596 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -452,6 +452,7 @@ struct CPUArchState { struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; int64_t last_icount; + int pending_trigger_hit; bool itrigger_enabled; =20 /* machine specific rdtime callback */ diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 6c69c2f796..ef2fafcbef 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -558,6 +558,34 @@ static void type2_breakpoint_remove(CPURISCVState *env= , target_ulong index) } } =20 +static int riscv_debug_find_breakpoint_trigger(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + CPUBreakpoint *bp; + + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (!(bp->flags & BP_CPU) || bp->pc !=3D env->pc) { + continue; + } + + for (int i =3D 0; i < RV_MAX_TRIGGERS; i++) { + int trigger_type =3D get_trigger_type(env, i); + + if (!trigger_common_match(env, trigger_type, i)) { + continue; + } + + if (bp =3D=3D env->cpu_breakpoint[i]) { + env->badaddr =3D bp->pc; + return i; + } + } + } + + return -1; +} + static void type2_reg_write(CPURISCVState *env, target_ulong index, int tdata_index, target_ulong val) { @@ -975,6 +1003,9 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + int hit =3D env->pending_trigger_hit; + + env->pending_trigger_hit =3D -1; =20 /* Triggers must not match or fire while in Debug Mode. */ if (env->debug_mode) { @@ -986,8 +1017,11 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) do_trigger_action(env, DBG_ACTION_BP); } } else { - if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { - do_trigger_action(env, DBG_ACTION_BP); + if (hit < 0) { + hit =3D riscv_debug_find_breakpoint_trigger(cs); + } + if (hit >=3D 0) { + do_trigger_action(env, hit); } } } @@ -996,47 +1030,9 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - CPUBreakpoint *bp; - target_ulong ctrl; - target_ulong pc; - int trigger_type; - int i; - - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { - trigger_type =3D get_trigger_type(env, i); =20 - if (!trigger_common_match(env, trigger_type, i)) { - continue; - } - - switch (trigger_type) { - case TRIGGER_TYPE_AD_MATCH: - ctrl =3D env->tdata1[i]; - pc =3D env->tdata2[i]; - - if ((ctrl & TYPE2_EXEC) && (bp->pc =3D=3D pc)) { - env->badaddr =3D pc; - return true; - } - break; - case TRIGGER_TYPE_AD_MATCH6: - ctrl =3D env->tdata1[i]; - pc =3D env->tdata2[i]; - - if ((ctrl & TYPE6_EXEC) && (bp->pc =3D=3D pc)) { - env->badaddr =3D pc; - return true; - } - break; - default: - /* other trigger types are not supported or irrelevant */ - break; - } - } - } - - return false; + env->pending_trigger_hit =3D riscv_debug_find_breakpoint_trigger(cs); + return env->pending_trigger_hit >=3D 0; } =20 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) @@ -1137,4 +1133,5 @@ void riscv_trigger_reset_hold(CPURISCVState *env) } =20 env->mcontext =3D 0; + env->pending_trigger_hit =3D -1; } --=20 2.53.0