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X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [PATCH v1 11/27] target/riscv: Add background CSRs accesses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 11 ++++ target/riscv/csr.c | 119 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 130 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index c898bb1102..9c27727e6f 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -169,6 +169,17 @@ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 =20 +/* Background CSRs */ +#define CSR_BSSTATUS 0x200 +#define CSR_BSIE 0x204 +#define CSR_BSTVEC 0x205 +#define CSR_BSSCRATCH 0x240 +#define CSR_BSEPC 0x241 +#define CSR_BSCAUSE 0x242 +#define CSR_BSTVAL 0x243 +#define CSR_BSIP 0x244 +#define CSR_BSATP 0x280 + /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 911f83ef51..c55eea44ec 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -799,6 +799,115 @@ static int write_hgatp(CPURISCVState *env, int csrno,= target_ulong val) return 0; } =20 +/* Background CSR Registers */ +static int read_bsstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->bsstatus; + return 0; +} + +static int write_bsstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bsstatus =3D val; + return 0; +} + +static int read_bsie(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->bsie; + return 0; +} + +static int write_bsie(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bsie =3D val; + return 0; +} + +static int read_bstvec(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->bstvec; + return 0; +} + +static int write_bstvec(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bstvec =3D val; + return 0; +} + +static int read_bsscratch(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->bsscratch; + return 0; +} + +static int write_bsscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bsscratch =3D val; + return 0; +} + +static int read_bsepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->bsepc; + return 0; +} + +static int write_bsepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bsepc =3D val; + return 0; +} + +static int read_bscause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->bscause; + return 0; +} + +static int write_bscause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bscause =3D val; + return 0; +} + +static int read_bstval(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->bstval; + return 0; +} + +static int write_bstval(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bstval =3D val; + return 0; +} + +static int read_bsip(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D (target_ulong)atomic_read(&env->bsip); + return 0; +} + +static int write_bsip(CPURISCVState *env, int csrno, target_ulong val) +{ + atomic_set(&env->bsip, val); + return 0; +} + +static int read_bsatp(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->bsatp; + return 0; +} + +static int write_bsatp(CPURISCVState *env, int csrno, target_ulong val) +{ + env->bsatp =3D val; + return 0; +} + /* Physical Memory Protection */ static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { @@ -987,6 +1096,16 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_HIDELEG] =3D { hmode, read_hideleg, write_hidel= eg }, [CSR_HGATP] =3D { hmode, read_hgatp, write_hgatp= }, =20 + [CSR_BSSTATUS] =3D { hmode, read_bsstatus, write_bssta= tus }, + [CSR_BSIE] =3D { hmode, read_bsie, write_bsie = }, + [CSR_BSTVEC] =3D { hmode, read_bstvec, write_bstve= c }, + [CSR_BSSCRATCH] =3D { hmode, read_bsscratch, write_bsscr= atch }, + [CSR_BSEPC] =3D { hmode, read_bsepc, write_bsepc= }, + [CSR_BSCAUSE] =3D { hmode, read_bscause, write_bscau= se }, + [CSR_BSTVAL] =3D { hmode, read_bstval, write_bstva= l }, + [CSR_BSIP] =3D { hmode, read_bsip, write_bsip = }, + [CSR_BSATP] =3D { hmode, read_bsatp, write_bsatp= }, + /* Physical Memory Protection */ [CSR_PMPCFG0 ... CSR_PMPADDR9] =3D { pmp, read_pmpcfg, write_pmpc= fg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] =3D { pmp, read_pmpaddr, write_pmpa= ddr }, --=20 2.21.0