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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Alejandro Jimenez , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PULL 69/75] amd_iommu: Refactor amdvi_page_walk() to use common code for page walk Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.43, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1759692516516116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Alejandro Jimenez Simplify amdvi_page_walk() by making it call the fetch_pte() helper that is already in use by the shadow page synchronization code. Ensures all code uses the same page table walking algorithm. Signed-off-by: Alejandro Jimenez Reviewed-by: Michael S. Tsirkin Message-ID: <20250919213515.917111-21-alejandro.j.jimenez@oracle.com> Signed-off-by: Michael S. Tsirkin --- hw/i386/amd_iommu.c | 77 ++++++++++++++++----------------------------- 1 file changed, 27 insertions(+), 50 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 1bda2a8ac3..b6851784fb 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -513,24 +513,6 @@ static inline uint8_t get_pte_translation_mode(uint64_= t pte) return (pte >> AMDVI_DEV_MODE_RSHIFT) & AMDVI_DEV_MODE_MASK; } =20 -static inline uint64_t pte_override_page_mask(uint64_t pte) -{ - uint8_t page_mask =3D 13; - uint64_t addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) >> 12; - /* find the first zero bit */ - while (addr & 1) { - page_mask++; - addr =3D addr >> 1; - } - - return ~((1ULL << page_mask) - 1); -} - -static inline uint64_t pte_get_page_mask(uint64_t oldlevel) -{ - return ~((1UL << ((oldlevel * 9) + 3)) - 1); -} - static inline uint64_t amdvi_get_pte_entry(AMDVIState *s, uint64_t pte_add= r, uint16_t devid) { @@ -1718,11 +1700,13 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, = uint64_t *dte, IOMMUTLBEntry *ret, unsigned perms, hwaddr addr) { - unsigned level, present, pte_perms, oldlevel; - uint64_t pte =3D dte[0], pte_addr, page_mask; + hwaddr page_mask, pagesize =3D 0; + uint8_t mode; + uint64_t pte; + int fetch_ret; =20 /* make sure the DTE has TV =3D 1 */ - if (!(pte & AMDVI_DEV_TRANSLATION_VALID)) { + if (!(dte[0] & AMDVI_DEV_TRANSLATION_VALID)) { /* * A DTE with V=3D1, TV=3D0 does not have a valid Page Table Root = Pointer. * An IOMMU processing a request that requires a table walk termin= ates @@ -1733,42 +1717,35 @@ static void amdvi_page_walk(AMDVIAddressSpace *as, = uint64_t *dte, return; } =20 - level =3D get_pte_translation_mode(pte); - if (level >=3D 7) { - trace_amdvi_mode_invalid(level, addr); + mode =3D get_pte_translation_mode(dte[0]); + if (mode >=3D 7) { + trace_amdvi_mode_invalid(mode, addr); return; } - if (level =3D=3D 0) { + if (mode =3D=3D 0) { goto no_remap; } =20 - /* we are at the leaf page table or page table encodes a huge page */ - do { - pte_perms =3D amdvi_get_perms(pte); - present =3D pte & 1; - if (!present || perms !=3D (perms & pte_perms)) { - amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); - trace_amdvi_page_fault(addr); - return; - } - /* go to the next lower level */ - pte_addr =3D pte & AMDVI_DEV_PT_ROOT_MASK; - /* add offset and load pte */ - pte_addr +=3D ((addr >> (3 + 9 * level)) & 0x1FF) << 3; - pte =3D amdvi_get_pte_entry(as->iommu_state, pte_addr, as->devfn); - if (!pte) { - return; - } - oldlevel =3D level; - level =3D get_pte_translation_mode(pte); - } while (level > 0 && level < 7); + /* Attempt to fetch the PTE to determine if a valid mapping exists */ + fetch_ret =3D fetch_pte(as, addr, dte[0], &pte, &pagesize); =20 - if (level =3D=3D 0x7) { - page_mask =3D pte_override_page_mask(pte); - } else { - page_mask =3D pte_get_page_mask(oldlevel); + /* + * If walking the page table results in an error of any type, returns = an + * empty PTE i.e. no mapping, or the permissions do not match, return = since + * there is no translation available. + */ + if (fetch_ret < 0 || !IOMMU_PTE_PRESENT(pte) || + perms !=3D (perms & amdvi_get_perms(pte))) { + + amdvi_page_fault(as->iommu_state, as->devfn, addr, perms); + trace_amdvi_page_fault(addr); + return; } =20 + /* A valid PTE and page size has been retrieved */ + assert(pagesize); + page_mask =3D ~(pagesize - 1); + /* get access permissions from pte */ ret->iova =3D addr & page_mask; ret->translated_addr =3D (pte & AMDVI_DEV_PT_ROOT_MASK) & page_mask; @@ -1780,7 +1757,7 @@ no_remap: ret->iova =3D addr & AMDVI_PAGE_MASK_4K; ret->translated_addr =3D addr & AMDVI_PAGE_MASK_4K; ret->addr_mask =3D ~AMDVI_PAGE_MASK_4K; - ret->perm =3D amdvi_get_perms(pte); + ret->perm =3D amdvi_get_perms(dte[0]); } =20 static void amdvi_do_translate(AMDVIAddressSpace *as, hwaddr addr, --=20 MST