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a="63369848" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="63369848" X-CSE-ConnectionGUID: cBVe/XFERcORWfdSNGMJfw== X-CSE-MsgGUID: 9+flY793TgqhbOopPdL9tA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="188747323" Date: Fri, 24 Oct 2025 15:18:07 +0800 From: Zhao Liu To: Ewan Hai Cc: pbonzini@redhat.com, qemu-devel@nongnu.org Subject: [PATCH] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Message-ID: References: <20250923021133.190725-1-ewanhai-oc@zhaoxin.com> <20250923021133.190725-4-ewanhai-oc@zhaoxin.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250923021133.190725-4-ewanhai-oc@zhaoxin.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.21; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1761288999249158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Many Intel and Zhaoxin CPUs enable CPUID 0x1f by default to encode CPU topology information. Add the "cpuid_0x1f" option to X86CPUDefinition to allow named CPU models to configure CPUID 0x1f from the start, thereby forcing 0x1f to be present for guest. With this option, there's no need to explicitly add v1 model to an unversioned CPU model for explicitly enabling the x-force-cpuid-0x1f property. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- target/i386/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 175054fdb322..56c1030a8627 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2307,6 +2307,12 @@ typedef struct X86CPUDefinition { int model; int stepping; uint8_t avx10_version; + /* + * Whether to present CPUID 0x1f by default. + * If true, encode CPU topology in 0x1f leaf even if there's no + * extended topology levels. + */ + bool cpuid_0x1f; FeatureWordArray features; const char *model_id; const CPUCaches *const cache_info; @@ -8092,6 +8098,10 @@ static void x86_cpu_load_model(X86CPU *cpu, const X8= 6CPUModel *model) &error_abort); } + if (def->cpuid_0x1f) { + object_property_set_bool(OBJECT(cpu), "x-force-cpuid-0x1f", def->c= puid_0x1f, + &error_abort); + } x86_cpu_apply_version_props(cpu, model); /* -- 2.34.1