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charset="utf-8" Split the file into clear machine and SoC sections. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 107 ++++++++++++++++++++++---------------------- 1 file changed, 54 insertions(+), 53 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 156a003642..9a0145b5b4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -399,6 +399,60 @@ static void riscv_sifive_u_init(MachineState *machine) &address_space_memory); } =20 +static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + return s->start_in_flash; +} + +static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **e= rrp) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D value; +} + +static void riscv_sifive_u_machine_instance_init(Object *obj) +{ + SiFiveUState *s =3D RISCV_U_MACHINE(obj); + + s->start_in_flash =3D false; + object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_= flash, + sifive_u_set_start_in_flash, NULL); + object_property_set_description(obj, "start-in-flash", + "Set on to tell QEMU's ROM to jump to = " \ + "flash. Otherwise QEMU will jump to DR= AM", + NULL); +} + + +static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; + mc->init =3D riscv_sifive_u_init; + mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; + mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus =3D mc->min_cpus; +} + +static const TypeInfo riscv_sifive_u_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("sifive_u"), + .parent =3D TYPE_MACHINE, + .class_init =3D riscv_sifive_u_machine_class_init, + .instance_init =3D riscv_sifive_u_machine_instance_init, + .instance_size =3D sizeof(SiFiveUState), +}; + +static void riscv_sifive_u_machine_init_register_types(void) +{ + type_register_static(&riscv_sifive_u_machine_typeinfo); +} + +type_init(riscv_sifive_u_machine_init_register_types) + static void riscv_sifive_u_soc_init(Object *obj) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -439,33 +493,6 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } =20 -static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - return s->start_in_flash; -} - -static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **e= rrp) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - s->start_in_flash =3D value; -} - -static void riscv_sifive_u_machine_instance_init(Object *obj) -{ - SiFiveUState *s =3D RISCV_U_MACHINE(obj); - - s->start_in_flash =3D false; - object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_= flash, - sifive_u_set_start_in_flash, NULL); - object_property_set_description(obj, "start-in-flash", - "Set on to tell QEMU's ROM to jump to = " \ - "flash. Otherwise QEMU will jump to DR= AM", - NULL); -} - static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -603,29 +630,3 @@ static void riscv_sifive_u_soc_register_types(void) } =20 type_init(riscv_sifive_u_soc_register_types) - -static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc =3D MACHINE_CLASS(oc); - - mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; - mc->init =3D riscv_sifive_u_init; - mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; - mc->min_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpus =3D mc->min_cpus; -} - -static const TypeInfo riscv_sifive_u_machine_typeinfo =3D { - .name =3D MACHINE_TYPE_NAME("sifive_u"), - .parent =3D TYPE_MACHINE, - .class_init =3D riscv_sifive_u_machine_class_init, - .instance_init =3D riscv_sifive_u_machine_instance_init, - .instance_size =3D sizeof(SiFiveUState), -}; - -static void riscv_sifive_u_machine_init_register_types(void) -{ - type_register_static(&riscv_sifive_u_machine_typeinfo); -} - -type_init(riscv_sifive_u_machine_init_register_types) --=20 2.25.1