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X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [RFC v1 22/23] target/riscv: Call the second stage MMU in virtualisation mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The qemu_log_mask(CPU_LOG_MMU,... calls trigger false positive checkpatch errors which are being ignored. Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 118 ++++++++++++++++++++++++++++++++------ 1 file changed, 99 insertions(+), 19 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 387c12547b..99091ed0fd 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -569,15 +569,23 @@ static void raise_mmu_exception(CPURISCVState *env, t= arget_ulong address, hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; hwaddr phys_addr; int prot; int mmu_idx =3D cpu_mmu_index(&cpu->env, false); =20 - if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_id= x, - true, false)) { + if (get_physical_address(env, &phys_addr, &prot, addr, 0, mmu_idx, + true, riscv_cpu_virt_enabled(env))) { return -1; } =20 + if (riscv_cpu_virt_enabled(env)) { + if (get_physical_address(env, &phys_addr, &prot, phys_addr, + 0, mmu_idx, false, true)) { + return -1; + } + } + return phys_addr; } =20 @@ -628,34 +636,106 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address,= int size, #ifndef CONFIG_USER_ONLY RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; + vaddr im_address; hwaddr pa =3D 0; int prot; + bool m_mode_two_stage =3D false; + bool hs_mode_two_stage =3D false; int ret =3D TRANSLATE_FAIL; =20 qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); =20 - ret =3D get_physical_address(env, &pa, &prot, address, access_type, mm= u_idx, - true, false); + /* + * Determine if we are in M mode and MPRV is set or in HS mode and SPR= V is + * set and we want to access a virtulisation address. + */ + if (riscv_has_ext(env, RVH)) { + m_mode_two_stage =3D env->priv =3D=3D PRV_M && + access_type !=3D MMU_INST_FETCH && + get_field(env->mstatus, MSTATUS_MPRV) && + get_field(env->mstatus, MSTATUS_MPV); + + hs_mode_two_stage =3D env->priv =3D=3D PRV_S && + !riscv_cpu_virt_enabled(env) && + access_type !=3D MMU_INST_FETCH && + get_field(env->hstatus, HSTATUS_SPRV) && + get_field(env->hstatus, HSTATUS_SPV); + } + + if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_sta= ge) { + /* Two stage lookup */ + ret =3D get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, true); =20 - qemu_log_mask(CPU_LOG_MMU, - "%s address=3D%" VADDR_PRIx " ret %d physical " TARGET_F= MT_plx - " prot %d\n", __func__, address, ret, pa, prot); + qemu_log_mask(CPU_LOG_MMU, + "%s 1st-stage address=3D%" VADDR_PRIx " ret %d physi= cal " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); =20 - if (riscv_feature(env, RISCV_FEATURE_PMP) && - !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { - ret =3D TRANSLATE_FAIL; - } - if (ret =3D=3D TRANSLATE_SUCCESS) { - tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); - return true; - } else if (probe) { - return false; + if (ret =3D=3D TRANSLATE_FAIL) { + if (!probe) { + raise_mmu_exception(env, address, access_type, true); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } + + /* Second stage lookup */ + im_address =3D pa; + + ret =3D get_physical_address(env, &pa, &prot, im_address, access_t= ype, mmu_idx, + false, true); + + qemu_log_mask(CPU_LOG_MMU, + "%s 2nd-stage address=3D%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, im_address, ret, pa, prot); + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_typ= e)) { + ret =3D TRANSLATE_FAIL; + } + + if (ret =3D=3D TRANSLATE_FAIL) { + /* + * Guest physical address translation failed, this is a HS + * level exception + */ + if (!probe) { + raise_mmu_exception(env, im_address | (address & (TARGET_P= AGE_SIZE - 1)), access_type, false); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } } else { - raise_mmu_exception(env, address, access_type, true); - riscv_raise_exception(env, cs->exception_index, retaddr); + /* Single stage lookup */ + ret =3D get_physical_address(env, &pa, &prot, address, access_type, + mmu_idx, true, false); + + qemu_log_mask(CPU_LOG_MMU, + "%s address=3D%" VADDR_PRIx " ret %d physical " + TARGET_FMT_plx " prot %d\n", + __func__, address, ret, pa, prot); + + if (riscv_feature(env, RISCV_FEATURE_PMP) && + !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_typ= e)) { + ret =3D TRANSLATE_FAIL; + } + + if (ret =3D=3D TRANSLATE_FAIL) { + if (!probe) { + raise_mmu_exception(env, address, access_type, true); + riscv_raise_exception(env, cs->exception_index, retaddr); + } + return ret; + } } + + tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, + prot, mmu_idx, TARGET_PAGE_SIZE); + return true; + #else switch (access_type) { case MMU_INST_FETCH: --=20 2.21.0