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x=1612055349; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WX8yZ6wKk7Bz2GCCNWa0L40pUiNjQzjDBbQ15tWCYBw=; b=mSSLifdaKrLMdtdz90GJQSHlp5NsBnZ2ExhPXn0Abf1L/Dvu/v6cVmD4 mnezZn8uG5vlGfBcQDuQOAkB1an9co6OdsAaFGAp+RKM/VMqfVOOVxvYj hGeN7JWT7P7nXH6zlbSDQXRl1Dl4bVil5V6lPGNmFLVBOUaRUSczifdhY K888Nmhh5DSJJNOAI37aSYzesyq7jiE8SHVlX8uWdLf/stzpFRWoA/qqL FwGGd8N38BSRm8eKYO1NYceF0DuxiJbQNXrdbqhP/KhO+Eij0relDItCl dwNs3Yj76nSEkSHdTT8RJJFtmJdI1R7o1SdgxuGFzCxvLmJniQjdk5F62 w==; IronPort-SDR: QRzq2wUkGVx64nFNWe71FyROw5KnxAx0lJQAnHCaiyJoD1gNRfbGz1BftIk3aQcRLHuLN3nWnH rmFQtMMU2v7oTnfl7ygDJzkzK2H1STDmXohqCRva7P9XgNWlsj5FACPpYgqIuB/GOtdT7RuMBu HNo+U/LrWwhH3X6+tgCirnI2wsnX0/WXdHXlA3WZdWpoh5vHxJ3K4S95RMOpwQe0vLO1mYXZnK n319MnWRhRWLXd8Hc5s0zNSTPa6gFC3l4kk6zMuS7kv+UNwDibfBL79NIFyMl9B3JA6vDdt3Sw 34g= X-IronPort-AV: E=Sophos;i="5.70,388,1574092800"; d="scan'208";a="128872449" IronPort-SDR: sBgEbgDXsOpGmMskRaE2Ibkj+zGY3ELNxT7TRNA7f4/nER+kNPgn2gQJzWazQPpkmacyfk4Gbi aTyq2Bw0bzDEIC8LKsFFT1pkBF5UeQdJbonmGhhJwiYYG+8C8B+MRC9ow/dAC10+NFl3sdr3Uy UKAxlnDVdUKA6fh+lVQRovHIafJMfrFf1k2HKRB1wyuEpQfFOCaBmEGCzLmEgbJkBw4VbqLqbD VawBb5y2wEMAIZyJZXHnFI9Oma/pwWF/n8Ilqaklob2WrWyRCtSDuYpw27HsU5DIwfJY/mZeYg E2JP8MCK2sBK+mvVziAOjFXZ IronPort-SDR: 9SybjkUcxiSjmDCtWbslr8DDunNFMKs25wqYzlyWpFY/KistsCxSRLEl3etCFjHBzZShTqR6RU 6OhuU4bGO9YKhMtSIKIj60//fX6L9Hqow/FDg77RgQDmyln4p3pNO6ryDMJHTfcG8OyZP2/Y00 6PF7OHaoNnTsKHBK9hM00NP5/e55/rgvARqCMZyyhMtC6U8BN9cHHnGTOj3+ogAHOdK+8N8QOI uKZO20cM2FR7os8Z/POgJrEr96qodtNxK9Ycql6AVZydl1rfSF3/rklPXukvGMrm8mxOKBsWjC Ync= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 14/35] target/riscv: Add virtual register swapping function Date: Fri, 31 Jan 2020 17:02:12 -0800 Message-Id: X-Mailer: git-send-email 2.25.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 11 +++++++ target/riscv/cpu_bits.h | 7 +++++ target/riscv/cpu_helper.c | 61 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 42720d65f9..5b889a0065 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -125,6 +125,7 @@ struct CPURISCVState { target_ulong mstatus; =20 target_ulong mip; + uint32_t miclaim; =20 target_ulong mie; @@ -166,6 +167,15 @@ struct CPURISCVState { target_ulong mtval2; target_ulong mtinst; =20 + /* HS Backup CSRs */ + target_ulong stvec_hs; + target_ulong sscratch_hs; + target_ulong sepc_hs; + target_ulong scause_hs; + target_ulong stval_hs; + target_ulong satp_hs; + target_ulong mstatus_hs; + target_ulong scounteren; target_ulong mcounteren; =20 @@ -296,6 +306,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index ad6479796c..a24654d137 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -553,4 +553,11 @@ #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP =20 +/* MIE masks */ +#define MIE_SEIE (1 << IRQ_S_EXT) +#define MIE_UEIE (1 << IRQ_U_EXT) +#define MIE_STIE (1 << IRQ_S_TIMER) +#define MIE_UTIE (1 << IRQ_U_TIMER) +#define MIE_SSIE (1 << IRQ_S_SOFT) +#define MIE_USIE (1 << IRQ_U_SOFT) #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1e28103500..e9d75b45d6 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -82,6 +82,67 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } =20 +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) +{ + target_ulong mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + bool current_virt =3D riscv_cpu_virt_enabled(env); + + g_assert(riscv_has_ext(env, RVH)); + +#if defined(TARGET_RISCV64) + mstatus_mask |=3D MSTATUS64_UXL; +#endif + + if (current_virt) { + /* Current V=3D1 and we are about to change to V=3D0 */ + env->vsstatus =3D env->mstatus & mstatus_mask; + env->mstatus &=3D ~mstatus_mask; + env->mstatus |=3D env->mstatus_hs; + + env->vstvec =3D env->stvec; + env->stvec =3D env->stvec_hs; + + env->vsscratch =3D env->sscratch; + env->sscratch =3D env->sscratch_hs; + + env->vsepc =3D env->sepc; + env->sepc =3D env->sepc_hs; + + env->vscause =3D env->scause; + env->scause =3D env->scause_hs; + + env->vstval =3D env->sbadaddr; + env->sbadaddr =3D env->stval_hs; + + env->vsatp =3D env->satp; + env->satp =3D env->satp_hs; + } else { + /* Current V=3D0 and we are about to change to V=3D1 */ + env->mstatus_hs =3D env->mstatus & mstatus_mask; + env->mstatus &=3D ~mstatus_mask; + env->mstatus |=3D env->vsstatus; + + env->stvec_hs =3D env->stvec; + env->stvec =3D env->vstvec; + + env->sscratch_hs =3D env->sscratch; + env->sscratch =3D env->vsscratch; + + env->sepc_hs =3D env->sepc; + env->sepc =3D env->vsepc; + + env->scause_hs =3D env->scause; + env->scause =3D env->vscause; + + env->stval_hs =3D env->sbadaddr; + env->sbadaddr =3D env->vstval; + + env->satp_hs =3D env->satp; + env->satp =3D env->vsatp; + } +} + bool riscv_cpu_virt_enabled(CPURISCVState *env) { if (!riscv_has_ext(env, RVH)) { --=20 2.25.0