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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=486123ee4=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/12 15:23:20 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, anup.patel@wdc.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" When performing a CSR access let's return a negative exception value on an error instead of -1. This will allow us to specify the exception in future patches. Signed-off-by: Alistair Francis --- target/riscv/csr.c | 46 ++++++++++++++++++++-------------------- target/riscv/op_helper.c | 18 ++++++++++------ 2 files changed, 35 insertions(+), 29 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7dc50e6299..197ce97e95 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -51,7 +51,7 @@ static int fs(CPURISCVState *env, int csrno) return 0; } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif return 0; @@ -73,7 +73,7 @@ static int ctr(CPURISCVState *env, int csrno) =20 if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif return 0; @@ -101,7 +101,7 @@ static int hmode(CPURISCVState *env, int csrno) } } =20 - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 static int pmp(CPURISCVState *env, int csrno) @@ -115,7 +115,7 @@ static int read_fflags(CPURISCVState *env, int csrno, t= arget_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D riscv_cpu_get_fflags(env); @@ -126,7 +126,7 @@ static int write_fflags(CPURISCVState *env, int csrno, = target_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -138,7 +138,7 @@ static int read_frm(CPURISCVState *env, int csrno, targ= et_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D env->frm; @@ -149,7 +149,7 @@ static int write_frm(CPURISCVState *env, int csrno, tar= get_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -161,7 +161,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, tar= get_ulong *val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif *val =3D (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) @@ -177,7 +177,7 @@ static int write_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong val) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mstatus |=3D MSTATUS_FS; #endif @@ -291,7 +291,7 @@ static int read_time(CPURISCVState *env, int csrno, tar= get_ulong *val) uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->rdtime_fn() + delta; @@ -304,7 +304,7 @@ static int read_timeh(CPURISCVState *env, int csrno, ta= rget_ulong *val) uint64_t delta =3D riscv_cpu_virt_enabled(env) ? env->htimedelta : 0; =20 if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D (env->rdtime_fn() + delta) >> 32; @@ -570,7 +570,7 @@ static int write_mcounteren(CPURISCVState *env, int csr= no, target_ulong val) static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v= al) { if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } *val =3D env->mcounteren; return 0; @@ -580,7 +580,7 @@ static int read_mscounteren(CPURISCVState *env, int csr= no, target_ulong *val) static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong v= al) { if (env->priv_ver < PRIV_VERSION_1_11_0) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } env->mcounteren =3D val; return 0; @@ -804,7 +804,7 @@ static int read_satp(CPURISCVState *env, int csrno, tar= get_ulong *val) } =20 if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } else { *val =3D env->satp; } @@ -821,7 +821,7 @@ static int write_satp(CPURISCVState *env, int csrno, ta= rget_ulong val) ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) { if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } else { if((val ^ env->satp) & SATP_ASID) { tlb_flush(env_cpu(env)); @@ -991,7 +991,7 @@ static int write_hgatp(CPURISCVState *env, int csrno, t= arget_ulong val) static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *va= l) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 #if defined(TARGET_RISCV32) @@ -1005,7 +1005,7 @@ static int read_htimedelta(CPURISCVState *env, int cs= rno, target_ulong *val) static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong va= l) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 #if defined(TARGET_RISCV32) @@ -1020,7 +1020,7 @@ static int write_htimedelta(CPURISCVState *env, int c= srno, target_ulong val) static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *v= al) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->htimedelta >> 32; @@ -1030,7 +1030,7 @@ static int read_htimedeltah(CPURISCVState *env, int c= srno, target_ulong *val) static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong v= al) { if (!env->rdtime_fn) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 env->htimedelta =3D deposit64(env->htimedelta, 32, 32, (uint64_t)val); @@ -1228,18 +1228,18 @@ int riscv_csrrw(CPURISCVState *env, int csrno, targ= et_ulong *ret_value, =20 if ((write_mask && read_only) || (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } #endif =20 /* ensure the CSR extension is enabled. */ if (!cpu->cfg.ext_icsr) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 /* check predicate */ if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) = < 0) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 /* execute combined read/write operation if it exists */ @@ -1249,7 +1249,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, =20 /* if no accessor exists then return failure */ if (!csr_ops[csrno].read) { - return -1; + return -RISCV_EXCP_ILLEGAL_INST; } =20 /* read old value */ diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 4b64bfe7d2..948d204793 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -43,8 +43,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulo= ng src, target_ulong csr) { target_ulong val =3D 0; - if (riscv_csrrw(env, csr, &val, src, -1) < 0) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + int ret =3D riscv_csrrw(env, csr, &val, src, -1); + + if (ret < 0) { + riscv_raise_exception(env, -ret, GETPC()); } return val; } @@ -53,8 +55,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulo= ng src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - if (riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0) < 0) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + int ret =3D riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0); + + if (ret < 0) { + riscv_raise_exception(env, -ret, GETPC()); } return val; } @@ -63,8 +67,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulo= ng src, target_ulong csr, target_ulong rs1_pass) { target_ulong val =3D 0; - if (riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0) < 0) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + int ret =3D riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0); + + if (ret < 0) { + riscv_raise_exception(env, -ret, GETPC()); } return val; } --=20 2.27.0