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IronPort-SDR: HfScqUDsMfjGSHNdN0UZuGEQq0P8+atXo0NAkdTfHaF2mnDyC+5kr0zgG70pdr6fj6UBLHjIiI wSAa3+cuA9McwRmN4tsXbWSx6zuKGTF2Rzp/JTy5oJoctVJegc3fjMtJyKaYqs9rDsH2Zyjcz/ H4mElgfB/TlUcH/V/1NKH+BvB6VPnl/wZ2PPT6lacXyFzvEOTz6cAEoBSwEzZQ8d4QyEg2slaH BBDkzhvK3r8Xrbiz/jQg9FTnaM2mfMsIGx7FpqojNTnnELDgFABF/VRjUDfjRldMY89qAo8jwA vZw= X-IronPort-AV: E=Sophos;i="5.73,446,1583164800"; d="scan'208";a="138744572" IronPort-SDR: ntWTFAl8DyLGBOoU6Y9gvLxuDXQYRd6aAEB7R6v5//66Tly0EprHNW/HgBzudy7FkIniclsBA4 KQWKrFszM+wAwrlh4qv7BdPC+8yA5aEZM= IronPort-SDR: JHQh9Tm1DmN/QU7rdSoBQBzDyOfZH5dm5ui38BiRJc8l0HZM3Js/cHRMWMVLcd7OgxSeyzkn9o WxK+bcWmIi+g== WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 04/11] target/riscv: Don't set PMP feature in the cpu init Date: Thu, 28 May 2020 15:14:17 -0700 Message-Id: X-Mailer: git-send-email 2.26.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=4104b2603=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/28 18:22:54 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The PMP is enabled by default via the "pmp" property so there is no need for us to set it in the init function. As all CPUs have PMP support just remove the set_feature() call in the CPU init functions. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8deba3d16d..406e8f37d7 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -142,7 +142,6 @@ static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_09_1); set_resetvec(env, DEFAULT_RSTVEC); - set_feature(env, RISCV_FEATURE_PMP); } =20 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) @@ -151,7 +150,6 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); - set_feature(env, RISCV_FEATURE_PMP); } =20 static void rv32imacu_nommu_cpu_init(Object *obj) @@ -160,7 +158,6 @@ static void rv32imacu_nommu_cpu_init(Object *obj) set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); - set_feature(env, RISCV_FEATURE_PMP); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } =20 @@ -170,7 +167,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj) set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); - set_feature(env, RISCV_FEATURE_PMP); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } =20 @@ -190,7 +186,6 @@ static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_09_1); set_resetvec(env, DEFAULT_RSTVEC); - set_feature(env, RISCV_FEATURE_PMP); } =20 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) @@ -199,7 +194,6 @@ static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); - set_feature(env, RISCV_FEATURE_PMP); } =20 static void rv64imacu_nommu_cpu_init(Object *obj) @@ -208,7 +202,6 @@ static void rv64imacu_nommu_cpu_init(Object *obj) set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); - set_feature(env, RISCV_FEATURE_PMP); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } =20 --=20 2.26.2