From nobody Sat Nov 23 18:20:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1730758733; cv=none; d=zohomail.com; s=zohoarc; b=KbB1pIuG0Z8hkPOFlMQ3dI5wEI9vMh+WnU20WFR5J5mgd76JfQHkBJs6ZMHDzMCSVgLctigtmpnJB7h/8pUNajJoF+b9rOP6t7Wspvy2nAM6eFvwXJTF0mfcNORdiZEPbOuU1KmWJeC2tQ/oEtkieLaqEHYk6Yl9HXlesKIC6oU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1730758733; h=Content-Type:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=EZiu8SQfJOHGDm+8cKKefPq3I7gZl7T0XsxLb3FiNFQ=; b=FRSEdbAq8j2JfwC+F/nvwughDN9O74jZNiurWeBp76kteTWlz6x+gHtOTjWygbTL5kdqcMQakoSwuWjH0BvzB/A9gzbc5KX6ruZbAD69pc27VUpv6YxxpYsRgrP86T//0Z1YMy7Y9cLGZaqYj9X04zp0H94OC3QLdxk9ADwITe0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 173075873303851.62533513402593; Mon, 4 Nov 2024 14:18:53 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1t85P2-0004FC-IG; Mon, 04 Nov 2024 17:18:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t85P0-0004Ez-Bp for qemu-devel@nongnu.org; Mon, 04 Nov 2024 17:18:26 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1t85Oy-0003OV-7C for qemu-devel@nongnu.org; Mon, 04 Nov 2024 17:18:25 -0500 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 7CDD05C44CF; Mon, 4 Nov 2024 22:17:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E76B3C4CECE; Mon, 4 Nov 2024 22:18:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1730758694; bh=/DPEM0nMUR7FEg053j9g2zBcZyeWCMCoIhkS1isDLqE=; h=Date:From:To:Subject:From; b=F+fzWfHFFn+R02bbQLTk7fissKCS3am+cGhArfDVCI/oBj+TlADKmmb/JhwiglRZb eT+DGtjsKmSkJfiB0QfEAVgm0nd5PM/ABqwcTxDhaAloAG6M1fZNwtmQ20OylPeJsx fRE57GclLXAhPYY9b9Tf0BREvu0M2kjl1uMA0Y/qk3a9YB0U93cQO20BtLrZdkQfq6 xVcwrmYlmcx5s9a5haeNmilVSoyMsw9mdWo5ckGUcRfnpp8riY5Gw2yS+K5Sn94pLd H5AyKWN2O5zV7ktIj0kcc/S5brBakOtLTiRyIjbffV8CJcrPUt9c+u4gKBobt+NF5f x9je7vFGnGvuA== Date: Mon, 4 Nov 2024 23:18:10 +0100 From: Helge Deller To: Peter Maydell , Richard Henderson , qemu-devel@nongnu.org Subject: [PATCH v2] target/hppa: Add CPU reset method Message-ID: MIME-Version: 1.0 Content-Disposition: inline Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=deller@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -46 X-Spam_score: -4.7 X-Spam_bar: ---- X-Spam_report: (-4.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.34, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1730758734655116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the CPU reset method, which resets all CPU registers and the TLB to zero. Then the CPU will switch to 32-bit mode (PSW_W bit is not set) and start execution at address 0xf0000004. Although we currently want to zero out all values in the CPUHPPAState struct, add the end_reset_fields marker in case the state structs gets extended with other variables later on which should not be reset. Signed-off-by: Helge Deller V2: (based on feedback by Peter Maydell) - Add end_reset_fields marker - call reset function in hppa_cpu_initfn() diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c38439c180..d12bf65021 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -194,13 +194,8 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error= **errp) =20 static void hppa_cpu_initfn(Object *obj) { - CPUState *cs =3D CPU(obj); - HPPACPU *cpu =3D HPPA_CPU(obj); - CPUHPPAState *env =3D &cpu->env; - - cs->exception_index =3D -1; - cpu_hppa_loaded_fr0(env); - cpu_hppa_put_psw(env, PSW_W); + /* inital values loaded via reset in hppa_cpu_reset_hold() */ + resettable_reset(obj, RESET_TYPE_COLD); } =20 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) @@ -235,15 +230,39 @@ static const TCGCPUOps hppa_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 +static void hppa_cpu_reset_hold(Object *obj, ResetType type) +{ + HPPACPU *cpu =3D HPPA_CPU(obj); + HPPACPUClass *scc =3D HPPA_CPU_GET_CLASS(cpu); + CPUHPPAState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + if (scc->parent_phases.hold) { + scc->parent_phases.hold(obj, type); + } + + memset(env, 0, offsetof(CPUHPPAState, end_reset_fields)); + cpu_set_pc(cs, 0xf0000004); + cpu_hppa_put_psw(env, hppa_is_pa20(env) ? PSW_W : 0); + cpu_hppa_loaded_fr0(env); + + cs->exception_index =3D -1; + cs->halted =3D 0; +} + static void hppa_cpu_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); CPUClass *cc =3D CPU_CLASS(oc); HPPACPUClass *acc =3D HPPA_CPU_CLASS(oc); + ResettableClass *rc =3D RESETTABLE_CLASS(oc); =20 device_class_set_parent_realize(dc, hppa_cpu_realizefn, &acc->parent_realize); =20 + resettable_class_set_parent_phases(rc, NULL, hppa_cpu_reset_hold, NULL, + &acc->parent_phases); + cc->class_by_name =3D hppa_cpu_class_by_name; cc->has_work =3D hppa_cpu_has_work; cc->mmu_index =3D hppa_cpu_mmu_index; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index e45ba50a59..32a674a8b8 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -263,6 +263,9 @@ typedef struct CPUArchState { IntervalTreeRoot tlb_root; =20 HPPATLBEntry tlb[HPPA_TLB_ENTRIES]; + + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; } CPUHPPAState; =20 /** @@ -281,6 +284,7 @@ struct ArchCPU { /** * HPPACPUClass: * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. * * An HPPA CPU model. */ @@ -288,6 +292,7 @@ struct HPPACPUClass { CPUClass parent_class; =20 DeviceRealize parent_realize; + ResettablePhases parent_phases; }; =20 #include "exec/cpu-all.h"