From nobody Sun Nov 24 09:10:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=kernel.org ARC-Seal: i=1; a=rsa-sha256; t=1725392838; cv=none; d=zohomail.com; s=zohoarc; b=Xeca7LYo+K461u2w0c5HutRBfZl/kf+bFR2K4aOZabBrEHxdl6WBl7ffU40Nswe68gkNDOkmBDjgJSsCrgVPHezyJJhWbdhjvQPUc0Ts10qqLASyjko+fL/KPDFP5WvyYZYLwcRfnr8lEKAVB+JttqoG/9RMsURY5PcVSuWwgEk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1725392838; h=Content-Type:Cc:Cc:Date:Date:From:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZvblouyJ39OmZIwBlp6W6oxjBfv0FxSzAoDIRPUMZPY=; b=I84P7+pXXzWy9SOrCoZkB2Jf8HF12Ss5ENCDcZxzK8pgbi0CFFKkMYYfPx3mRkfTJoqjy0ud3Dr2ZW7vVNKtWeWDMhYOhhJtzeil3Q/TpLxHBeB/cjdFtbg8jpQKV2Jt1VdyiDnuTOD43RKzcP+S4+Us5tdbgczRQfgb6uASVC4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=quarantine dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1725392838168892.3135962829525; Tue, 3 Sep 2024 12:47:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1slZU5-0003Lj-KV; Tue, 03 Sep 2024 15:46:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1slZU3-0003L9-Fd for qemu-devel@nongnu.org; Tue, 03 Sep 2024 15:46:35 -0400 Received: from nyc.source.kernel.org ([147.75.193.91]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1slZU1-0001zn-A9 for qemu-devel@nongnu.org; Tue, 03 Sep 2024 15:46:34 -0400 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id ADD5CA43D57; Tue, 3 Sep 2024 19:46:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3770CC4CEC4; Tue, 3 Sep 2024 19:46:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725392791; bh=ysZPsnNd3kpF3n+8IozMgz2v1zNkNppqWJ1IaiWjDiM=; h=Date:From:To:Cc:Subject:From; b=lHbsP6K+Z+Yw07JvPU9U4ZHcRYoP+zNZqQ73tjeOl7IZNpJY5BW13Y7HHvb+e5ost NIvBGIY/Tkn6rdQVrLMahHOxlojmZPltdPzvw1L5Sq5gFEfK9Yxj2zF22//IctGzhG AItQsKsge0o1h/VqBKlwZxbyeq9ZZ+862siqPSNkF/VdVpn3+jtgEiCCIqUK8UlRIP 4Ax8YVbpYqcHlswj4OVLJBl+DVtb3FQMGb7iolrwyzniriKuzA7pSBjHQQlEuQxRuQ qZ7uLktnrhXEU31gczK+OQWINpOA8U3C3hP6dZ/CaivRhoORNb/ZWSHR4UnXgNrVs8 SY6x4SraNBIYQ== Date: Tue, 3 Sep 2024 21:46:27 +0200 From: Helge Deller To: Richard Henderson , qemu-devel@nongnu.org, Philippe =?iso-8859-15?Q?Mathieu-Daud=E9?= Cc: linux-parisc@vger.kernel.org Subject: [PATCH v2] target/hppa: Fix PSW V-bit packaging in cpu_hppa_get for hppa64 Message-ID: MIME-Version: 1.0 Content-Disposition: inline Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=147.75.193.91; envelope-from=deller@kernel.org; helo=nyc.source.kernel.org X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.142, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @kernel.org) X-ZM-MESSAGEID: 1725392840842116600 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" While adding hppa64 support, the psw_v variable got extended from 32 to 64 bits. So, when packaging the PSW-V bit from the psw_v variable for interru= pt processing, check bit 31 instead the 63th (sign) bit. This fixes a hard to find Linux kernel boot issue where the loss of the PSW= -V bit due to an ITLB interruption in the middle of a series of ds/addc instructions (from the divU milicode library) generated the wrong division result and thus triggered a Linux kernel crash. Link: https://lore.kernel.org/lkml/718b8afe-222f-4b3a-96d3-93af0e4ceff1@roe= ck-us.net/ Reported-by: Guenter Roeck Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Tested-by: Guenter Roeck Fixes: 931adff31478 ("target/hppa: Update cpu_hppa_get/put_psw for hppa64") Cc: qemu-stable@nongnu.org # v8.2+ --- v2: - added change to cpu.h (as requested by Richard) - added Richards R-b - added stable CC tag diff --git a/target/hppa/helper.c b/target/hppa/helper.c index b79ddd8184..d4b1a3cd5a 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -53,7 +53,7 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env) } =20 psw |=3D env->psw_n * PSW_N; - psw |=3D (env->psw_v < 0) * PSW_V; + psw |=3D ((env->psw_v >> 31) & 1) * PSW_V; psw |=3D env->psw | env->psw_xb; =20 return psw; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 56d9568d6c..43074d80bf 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -211,7 +211,7 @@ typedef struct CPUArchState { uint32_t psw; /* All psw bits except the following: */ uint32_t psw_xb; /* X and B, in their normal positions */ target_ulong psw_n; /* boolean */ - target_long psw_v; /* in most significant bit */ + target_long psw_v; /* in bit 31 */ =20 /* Splitting the carry-borrow field into the MSB and "the rest", allows * for "the rest" to be deleted when it is unused, but the MSB is in u= se.