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Date: Sat, 28 Dec 2024 00:17:33 +0100
From: Helge Deller <deller@kernel.org>
To: peter.maydell@linaro.org, richard.henderson@linaro.org,
qemu-devel@nongnu.org
Subject: [PATCH v3] target/hppa: Add CPU reset method
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Add the CPU reset method, which resets all CPU registers and the TLB to
zero. Then the CPU will switch to 32-bit mode (PSW_W bit is not set) and
start execution at address 0xf0000004.
Although we currently want to zero out all values in the CPUHPPAState
struct, add the end_reset_fields marker in case the state structs gets
extended with other variables later on which should not be reset.
Signed-off-by: Helge Deller <deller@gmx.de>
V3:
- Call reset function from hppa_machine_reset() instead
V2:
- Add end_reset_fields marker
- call reset function in hppa_cpu_initfn()
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c
index a31dc32a9f..05fd43ce9c 100644
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
--- a/hw/hppa/machine.c
+++ b/hw/hppa/machine.c
@@ -655,12 +655,12 @@ static void hppa_machine_reset(MachineState *ms, Rese=
tType type)
for (i =3D 0; i < smp_cpus; i++) {
CPUState *cs =3D CPU(cpu[i]);
=20
+ /* reset CPU */
+ resettable_reset(OBJECT(cs), RESET_TYPE_COLD);
+
cpu_set_pc(cs, firmware_entry);
cpu[i]->env.psw =3D PSW_Q;
cpu[i]->env.gr[5] =3D CPU_HPA + i * 0x1000;
-
- cs->exception_index =3D -1;
- cs->halted =3D 0;
}
=20
/* already initialized by machine_hppa_init()? */
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index c38439c180..b908cf65c6 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -235,15 +235,39 @@ static const TCGCPUOps hppa_tcg_ops =3D {
#endif /* !CONFIG_USER_ONLY */
};
=20
+static void hppa_cpu_reset_hold(Object *obj, ResetType type)
+{
+ HPPACPU *cpu =3D HPPA_CPU(obj);
+ HPPACPUClass *scc =3D HPPA_CPU_GET_CLASS(cpu);
+ CPUHPPAState *env =3D &cpu->env;
+ CPUState *cs =3D CPU(cpu);
+
+ if (scc->parent_phases.hold) {
+ scc->parent_phases.hold(obj, type);
+ }
+
+ memset(env, 0, offsetof(CPUHPPAState, end_reset_fields));
+ cpu_set_pc(cs, 0xf0000004);
+ cpu_hppa_put_psw(env, hppa_is_pa20(env) ? PSW_W : 0);
+ cpu_hppa_loaded_fr0(env);
+
+ cs->exception_index =3D -1;
+ cs->halted =3D 0;
+}
+
static void hppa_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc =3D DEVICE_CLASS(oc);
CPUClass *cc =3D CPU_CLASS(oc);
HPPACPUClass *acc =3D HPPA_CPU_CLASS(oc);
+ ResettableClass *rc =3D RESETTABLE_CLASS(oc);
=20
device_class_set_parent_realize(dc, hppa_cpu_realizefn,
&acc->parent_realize);
=20
+ resettable_class_set_parent_phases(rc, NULL, hppa_cpu_reset_hold, NULL,
+ &acc->parent_phases);
+
cc->class_by_name =3D hppa_cpu_class_by_name;
cc->has_work =3D hppa_cpu_has_work;
cc->mmu_index =3D hppa_cpu_mmu_index;
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index e45ba50a59..32a674a8b8 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -263,6 +263,9 @@ typedef struct CPUArchState {
IntervalTreeRoot tlb_root;
=20
HPPATLBEntry tlb[HPPA_TLB_ENTRIES];
+
+ /* Fields up to this point are cleared by a CPU reset */
+ struct {} end_reset_fields;
} CPUHPPAState;
=20
/**
@@ -281,6 +284,7 @@ struct ArchCPU {
/**
* HPPACPUClass:
* @parent_realize: The parent class' realize handler.
+ * @parent_phases: The parent class' reset phase handlers.
*
* An HPPA CPU model.
*/
@@ -288,6 +292,7 @@ struct HPPACPUClass {
CPUClass parent_class;
=20
DeviceRealize parent_realize;
+ ResettablePhases parent_phases;
};
=20
#include "exec/cpu-all.h"