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charset="utf-8" The correct A20 masking is done if paging is enabled (protected mode) but it seems to have been forgotten in real mode. For example from the AMD64 APM V= ol. 2 section 1.2.4: > If the sum of the segment base and effective address carries over into bi= t 20, > that bit can be optionally truncated to mimic the 20-bit address wrapping= of the > 8086 processor by using the A20M# input signal to mask the A20 address bi= t. Most BIOSes will enable the A20 line on boot, but I found by disabling the = A20 line afterwards, the correct wrapping wasn't taking place. `handle_mmu_fault' in target/i386/tcg/sysemu/excp_helper.c seems to be the = culprit. In real mode, it fills the TLB with the raw unmasked address. However, for = the protected mode, the `mmu_translate' function does the correct A20 masking. The fix then should be to just apply the A20 mask in the first branch of th= e if statement. Signed-off-by: Stephen Michael Jothen --- target/i386/tcg/sysemu/excp_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index e1b6d88683..48feba7e75 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -359,6 +359,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, i= nt size, CPUX86State *env =3D &cpu->env; int error_code =3D PG_ERROR_OK; int pg_mode, prot, page_size; + int32_t a20_mask; hwaddr paddr; hwaddr vaddr; =20 @@ -368,7 +369,8 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, i= nt size, #endif =20 if (!(env->cr[0] & CR0_PG_MASK)) { - paddr =3D addr; + a20_mask =3D x86_get_a20_mask(env); + paddr =3D addr & a20_mask; #ifdef TARGET_X86_64 if (!(env->hflags & HF_LMA_MASK)) { /* Without long mode we can only address 32bits in real mode */ --=20 2.30.1 (Apple Git-130)