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envelope-from=ishii.shuuichir@fujitsu.com; helo=esa20.fujitsucc.c3s2.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "peter.maydell@linaro.org" , "richard.henderson@linaro.org" , "qemu-devel@nongnu.org" , "qemu-arm@nongnu.org" , "ishii.shuuichir@fujitsu.com" , "philmd@redhat.com" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @fujitsu.onmicrosoft.com) X-ZM-MESSAGEID: 1630053097682100001 Thank you, Andrew, for creating the patches. And thank you all for your comments. I have applied the suggested v2 patch series by andrew locally,=20 and reviewed the next version of the a64fx patch series as follows.=20 I would appreciate if you could comment on whether there are any problems with the fixes before I post the next version of the patch. (The a64fx patch series to be posted later will be split as previously post= ed.) ---------------------------------------------------------------------------= --------------------- diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 59acf0eeaf..850787495b 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -55,6 +55,7 @@ Supported guest CPU types: - ``cortex-a53`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) +- ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 81eda46b0b..10286d3fd6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -200,6 +200,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2866dd7658..2d9f779cb6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1350,10 +1350,12 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error *= *errp) Error *local_err =3D NULL; if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - arm_cpu_sve_finalize(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; + if (!arm_feature(&cpu->env, ARM_FEATURE_A64FX)) { + arm_cpu_sve_finalize(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } } /* diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cc645b5742..bf8d9ddaa1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2149,6 +2149,7 @@ enum arm_features { ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ + ARM_FEATURE_A64FX, /* Fujitsu A64FX processor */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2f0cbddab5..18e813264a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -841,10 +841,80 @@ static void aarch64_max_initfn(Object *obj) cpu_max_set_sve_max_vq, NULL, NULL); } +static void a64fx_cpu_set_sve(Object *obj) +{ + int i; + Error *errp =3D NULL; + ARMCPU *cpu =3D ARM_CPU(obj); + /* Suppport of A64FX's vector length are 128,256 and 512bit only */ + const char *vl[] =3D {"sve128", "sve256", "sve512"}; + + object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); + object_property_set_bool(obj, "sve", true, &errp); + + for(i =3D 0; i sve_vq_supported, ARM_MAX_VQ); + set_bit(0, cpu->sve_vq_supported); /* 128bit */ + set_bit(1, cpu->sve_vq_supported); /* 256bit */ + set_bit(3, cpu->sve_vq_supported); /* 512bit */ + + cpu->sve_max_vq =3D find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; +} + +static void aarch64_a64fx_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,a64fx"; + set_feature(&cpu->env, ARM_FEATURE_A64FX); + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x461f0010; + cpu->revidr =3D 0x00000000; + cpu->ctr =3D 0x86668006; + cpu->reset_sctlr =3D 0x30000180; + cpu->isar.id_aa64pfr0 =3D 0x0000000101111111; /* No RAS Extensions */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000000; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408; + cpu->isar.id_aa64dfr1 =3D 0x0000000000000000; + cpu->id_aa64afr0 =3D 0x0000000000000000; + cpu->id_aa64afr1 =3D 0x0000000000000000; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000001122; + cpu->isar.id_aa64mmfr1 =3D 0x0000000011212100; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011; + cpu->isar.id_aa64isar0 =3D 0x0000000010211120; + cpu->isar.id_aa64isar1 =3D 0x0000000000010001; + cpu->isar.id_aa64zfr0 =3D 0x0000000000000000; + cpu->clidr =3D 0x0000000080000023; + cpu->ccsidr[0] =3D 0x7007e01c; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x2007e01c; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07c; /* 8MB L2 cache */ + cpu->dcz_blocksize =3D 6; /* 256 bytes */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* Set SVE properties */ + a64fx_cpu_set_sve(obj); + + /* TODO: Add A64FX specific HPC extension registers */ +} + static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, }; diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 8252b85bb8..bf30bee462 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -472,6 +472,11 @@ static void test_query_cpu_model_expansion(const void = *data) assert_has_feature_enabled(qts, "max", "sve128"); assert_has_feature_enabled(qts, "cortex-a57", "pmu"); assert_has_feature_enabled(qts, "cortex-a57", "aarch64"); + assert_has_feature_enabled(qts, "a64fx", "pmu"); + assert_has_feature_enabled(qts, "a64fx", "aarch64"); + assert_has_feature_enabled(qts, "a64fx", "sve"); + assert_has_feature_enabled(qts, "a64fx", "sve128"); + assert_has_feature_enabled(qts, "a64fx", "sve256"); + assert_has_feature_enabled(qts, "a64fx", "sve512"); sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); ---------------------------------------------------------------------------= --------------------- By the way, There is one thing that bothers me about the above modification. The A64FX supports only 128-bit, 256-bit, and 512-bit SVE vector lengths, b= ut the The following process in the arm_cpu_sve_finalize() function sets all bits = of cpu->sve_vq_map to 1. /* Set all bits not explicitly set within sve-max-vq. */ bitmap_complement(tmp, cpu->sve_vq_init, max_vq); bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); As a result, enter a routine where the following process will be executed. error_setg(errp, "cannot set sve-max-vq=3D%d", cpu->sve_max_vq); Therefore, We have applied the following fix, is this ok? ---------------------------------------------------------------------------= --------------------- --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1350,10 +1350,12 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error *= *errp) Error *local_err =3D NULL; if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - arm_cpu_sve_finalize(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; + if (!arm_feature(&cpu->env, ARM_FEATURE_A64FX)) { + arm_cpu_sve_finalize(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } } ---------------------------------------------------------------------------= --------------------- Please your comments if we have misunderstood. Best regards. > -----Original Message----- > From: Andrew Jones > Sent: Tuesday, August 24, 2021 1:07 AM > To: qemu-devel@nongnu.org; qemu-arm@nongnu.org > Cc: Ishii, Shuuichirou/=E7=9F=B3=E4=BA=95 =E5=91=A8=E4=B8=80=E9=83=8E ; > richard.henderson@linaro.org; peter.maydell@linaro.org; philmd@redhat.com > Subject: [PATCH v2 0/4] target/arm/cpu: Introduce sve_vq_supported bitmap >=20 > v2: > - Completed testing > - Removed extra space in an error message > - Added Phil's r-b's >=20 > While reviewing the new A64FX CPU type it became clear that CPU types sho= uld > be able to specify which SVE vector lengths are supported. This series ad= ds a new > bitmap member to ARMCPU and modifies arm_cpu_sve_finalize() to validate > inputs against it. > So far we only need to set the bitmap for the 'max' CPU type though and, = since it > supports all vector lengths, we just fill the whole thing. >=20 > This series was inspired by Richard Henderson's suggestion to replace > arm_cpu_sve_finalize's kvm_supported bitmap with something that could be > shared with TCG. >=20 > Thanks, > drew >=20 >=20 > Andrew Jones (4): > target/arm/cpu: Introduce sve_vq_supported bitmap > target/arm/kvm64: Ensure sve vls map is completely clear > target/arm/cpu64: Replace kvm_supported with sve_vq_supported > target/arm/cpu64: Validate sve vector lengths are supported >=20 > target/arm/cpu.h | 4 ++ > target/arm/cpu64.c | 118 > +++++++++++++++++++++------------------------ > target/arm/kvm64.c | 2 +- > 3 files changed, 61 insertions(+), 63 deletions(-) >=20 > -- > 2.31.1