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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:111:f400:feae::803; envelope-from=taisei1212@outlook.jp; helo=APC01-PSA-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @OUTLOOK.JP) X-ZM-MESSAGEID: 1720871760153116600 Content-Type: text/plain; charset="utf-8" Before this commit, there are 3 problems about HPET timer interrupts. First, HPET periodic timers cause a too early interrupt before HPET main counter value reaches a value written its comparator value register. Second, disabled HPET timers whose comparator value register is not 0xffffffffffffffff cause wrong interrupts. Third, enabled HPET timers whose comparator value register is 0xffffffffffffffff don't cause any interrupts. About the first one, for example, an HPET driver writes 0x00000000aaaaaaaa to an HPET periodic timer comparator value register. As a result, the register becomes 0xffffffffaaaaaaaa because writing to the higher 32 bits of the register doesn't affect itself in periodic mode. (see "case HPET_TN_CMP + 4" of "hpet_ram_write" function.) And "timer->period" which means interrupt period in periodic mode becomes 0xaaaaaaaa. Next, the HPET driver sets the HPET_CFG_ENABLE flag to start the main counter. The comparator value register (0xffffffffaaaaaaaa) indicate the next interrupt time. The period (0xaaaaaaaa) is added to the comparator value register at "hpet_timer" function because "hpet_time_after64" function returns true when the main counter is small. So, the first interrupt is planned when the main counter is 0x0000000055555554, but the first interrupt should occur when the main counter is 0x00000000aaaaaaaa. To solve this problem, I fix "case HPET_TN_CMP + 4" of "hpet_ram_write" function to ensure that writings to higher 32 bits of a comparator value register reflect itself even if in periodic mode. About the other two problems, it was decided by comparator value whether each timer is enabled, but it should be decided by "timer_enabled" function which confirm "HPET_TN_ENABLE" flag. To solve these problems, I fix the code to decide correctly whether each timer is enabled. After this commit, the 3 problems are solved. First, HPET periodic timers cause the first interrupt when the main counter value reaches a value written its comparator value register. Second, disabled HPET timers never cause any interrupt. Third, enabled HPET timers cause interrupts correctly even if an HPET driver writes 0xffffffffffffffff to its comparator value register. Signed-off-by: TaiseiIto --- Changes in v2: - Reflect writings to higher 32 bits of a comparator value register rather than clearing these bits. - Fix wrong indents. - Link to v1: https://lore.kernel.org/qemu-devel/TY0PR0101MB4285838139BC56D= EC3D1CCFDA4CE2@TY0PR0101MB4285.apcprd01.prod.exchangelabs.com/ hw/timer/hpet.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 01efe4885d..4b6352e257 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -552,6 +552,10 @@ static void hpet_ram_write(void *opaque, hwaddr addr, timer->period =3D (timer->period & 0xffffffff00000000ULL) | new_val; } + /* + * FIXME: on a 64-bit write, HPET_TN_SETVAL should apply to the + * high bits part as well. + */ timer->config &=3D ~HPET_TN_SETVAL; if (hpet_enabled(s)) { hpet_set_timer(timer); @@ -562,20 +566,22 @@ static void hpet_ram_write(void *opaque, hwaddr addr, if (!timer_is_periodic(timer) || (timer->config & HPET_TN_SETVAL)) { timer->cmp =3D (timer->cmp & 0xffffffffULL) | new_val << 3= 2; - } else { + } + if (timer_is_periodic(timer)) { /* * FIXME: Clamp period to reasonable min value? * Clamp period to reasonable max value */ - new_val &=3D (timer->config & HPET_TN_32BIT ? ~0u : ~0ull)= >> 1; + new_val =3D MIN(new_val, ~0u >> 1); + timer->cmp =3D (timer->cmp & 0xffffffffULL) | new_val << 3= 2; timer->period =3D (timer->period & 0xffffffffULL) | new_val << 32; - } - timer->config &=3D ~HPET_TN_SETVAL; - if (hpet_enabled(s)) { - hpet_set_timer(timer); - } - break; + } + timer->config &=3D ~HPET_TN_SETVAL; + if (hpet_enabled(s)) { + hpet_set_timer(timer); + } + break; case HPET_TN_ROUTE: timer->fsb =3D (timer->fsb & 0xffffffff00000000ULL) | new_val; break; @@ -599,7 +605,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr, s->hpet_offset =3D ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_= CLOCK_VIRTUAL); for (i =3D 0; i < s->num_timers; i++) { - if ((&s->timer[i])->cmp !=3D ~0ULL) { + if (hpet_enabled(s)) { hpet_set_timer(&s->timer[i]); } } --=20 2.34.1