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b=wlfm6XwKCVBiGaptvoL6UldqW6VWvaYVfRJKG+TCAJ+sYmh3ZRTnT6ZhZi4xxxcaaZByRJ+e+/1KdZD1eavNONa7j6I1b1az0JR3isD7vCd9kHdc8HtTqDPVh2NmHEatjXc2Q+AWf+1oomW3+n2GI1Qz2ytHvGE6Vt+X6sCkT7YVM/SnvHOlXQ7mpehgswZbIOhX6RNsBJ/oeCPKMNPySSBDK6AaXc7bHubzZK+eWBACKr/U0FNbVqUUhxhNmBnEUC5RCF3UekM/VFD3H8biRo2F7X/mkh04Dy9058FFA+rQOhPPX/OjluhJ8RLXWh64AazY/nZp42U3BEWToQ8dUw== From: =?utf-8?B?WXVtaW5nIFl1LU1pbmcgQ2hhbmco5by16IKy6YqYKQ==?= To: Alistair Francis CC: "qemu-riscv@nongnu.org" , "qemu-devel@nongnu.org" , "palmer@dabbelt.com" , "alistair.francis@wdc.com" , "bin.meng@windriver.com" , "liwei1518@gmail.com" , "dbarboza@ventanamicro.com" , "zhiwei_liu@linux.alibaba.com" Subject: RE: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR Thread-Topic: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR Thread-Index: AQHahZXSHmyMrDTHa0+LBGZgOV4lk7G15YqAgAAEWaA= Date: Mon, 3 Jun 2024 06:00:37 +0000 Message-ID: References: <20240403070823.80897-1-yumin686@andestech.com> In-Reply-To: Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=andestech.com; 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envelope-from=yumin686@andestech.com; helo=APC01-PSA-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @andestech.com) X-ZM-MESSAGEID: 1717394535482100005 Hi Alistair, I think we need the following patch to fix this issue: From 6175c9aee103e40b5a5da587f659563de93b3d85 Mon Sep 17 00:00:00 2001 From: Alvin Chang Date: Thu, 18 Apr 2024 14:52:36 +0800 Subject: [PATCH] target/riscv: Fix GDB can not read the read-only CSR From commit 563581cb60, use riscv_csrrw() to read a read-only CSR will lead to exception. Fix it by calling riscv_csrr() when GDB wants to read a read-only CSR. Signed-off-by: Alvin Chang --- target/riscv/csr.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7aab267916..96accc1549 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -4625,7 +4625,11 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env,= int csrno, #if !defined(CONFIG_USER_ONLY) env->debugger =3D true; #endif - ret =3D riscv_csrrw(env, csrno, ret_value, new_value, write_mask); + if (!write_mask) { + ret =3D riscv_csrr(env, csrno, ret_value); + } else { + ret =3D riscv_csrrw(env, csrno, ret_value, new_value, write_mask); + } #if !defined(CONFIG_USER_ONLY) env->debugger =3D false; #endif -- 2.34.1 Best regards, Yuming -----Original Message----- From: Alistair Francis Sent: Monday, June 3, 2024 1:39 PM To: Yuming Yu-Ming Chang(=E5=BC=B5=E8=82=B2=E9=8A=98) Cc: qemu-riscv@nongnu.org; qemu-devel@nongnu.org; palmer@dabbelt.com; alist= air.francis@wdc.com; bin.meng@windriver.com; liwei1518@gmail.com; dbarboza@= ventanamicro.com; zhiwei_liu@linux.alibaba.com Subject: Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC w= rites a read-only CSR [EXTERNAL MAIL] On Wed, Apr 3, 2024 at 5:10=E2=80=AFPM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a reg= ister > holding a zero value other than x0, the instruction will still attempt to= write > the unmodified value back to the CSR and will cause any attendant side ef= fects. > > So if CSRRS or CSRRC tries to write a read-only CSR with rs1 which specif= ies > a register holding a zero value, an illegal instruction exception should = be > raised. > > Signed-off-by: Yu-Ming Chang This fails the GitLab CI tests https://gitlab.com/qemu-project/qemu/-/jobs/6953349448 ERROR:../tests/plugin/insn.c:58:vcpu_init: assertion failed: (count > 0) timeout: the monitored command dumped core Aborted make[1]: *** [Makefile:178: run-plugin-catch-syscalls-with-libinsn.so] Erro= r 134 make: *** [/builds/qemu-project/qemu/tests/Makefile.include:56: run-tcg-tests-riscv64-linux-user] Error 2 #0 riscv_gdb_get_csr (cs=3D, buf=3D0x5555558e7f50, n=3D3072) at ../src/target/riscv/gdbstub.c:183 #1 0x00007ffff7fb7841 in vcpu_init (id=3D, vcpu_index=3D) at ../src/tests/plugin/insn.c:57 #2 0x000055555569ef1a in plugin_vcpu_cb__simple (cpu=3D0x5555558fb820, ev=3D) at ../src/plugins/core.c:111 After 182 result =3D riscv_csrrw_debug(env, n, &val, 0, 0); result =3D=3D 2. I haven't had much luck reproducing this locally, so I don't have a great idea of why it isn't working. I suspect you need to ignore the checks for debug accesses Alistair > --- > Hi maintainers, > Do I need to make any further improvements to this patch? > > Best regards, > Yuming > > target/riscv/cpu.h | 4 ++++ > target/riscv/csr.c | 51 ++++++++++++++++++++++++++++++++++++---- > target/riscv/op_helper.c | 6 ++--- > 3 files changed, 53 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 3b1a02b944..99006bdb45 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -710,6 +710,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *= pc, > void riscv_cpu_update_mask(CPURISCVState *env); > bool riscv_cpu_is_32bit(RISCVCPU *cpu); > > +RISCVException riscv_csrr(CPURISCVState *env, int csrno, > + target_ulong *ret_value); > RISCVException riscv_csrrw(CPURISCVState *env, int csrno, > target_ulong *ret_value, > target_ulong new_value, target_ulong write_ma= sk); > @@ -742,6 +744,8 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVSta= te *env, int csrno, > target_ulong new_value, > target_ulong write_mask); > > +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, > + Int128 *ret_value); > RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, > Int128 *ret_value, > Int128 new_value, Int128 write_mask); > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 726096444f..35662e1777 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -4312,7 +4312,7 @@ static RISCVException rmw_seed(CPURISCVState *env, = int csrno, > > static inline RISCVException riscv_csrrw_check(CPURISCVState *env, > int csrno, > - bool write_mask) > + bool write) > { > /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fail= s */ > bool read_only =3D get_field(csrno, 0xC00) =3D=3D 3; > @@ -4334,7 +4334,7 @@ static inline RISCVException riscv_csrrw_check(CPUR= ISCVState *env, > } > > /* read / write check */ > - if (write_mask && read_only) { > + if (write && read_only) { > return RISCV_EXCP_ILLEGAL_INST; > } > > @@ -4421,11 +4421,22 @@ static RISCVException riscv_csrrw_do64(CPURISCVSt= ate *env, int csrno, > return RISCV_EXCP_NONE; > } > > +RISCVException riscv_csrr(CPURISCVState *env, int csrno, > + target_ulong *ret_value) > +{ > + RISCVException ret =3D riscv_csrrw_check(env, csrno, false); > + if (ret !=3D RISCV_EXCP_NONE) { > + return ret; > + } > + > + return riscv_csrrw_do64(env, csrno, ret_value, 0, 0); > +} > + > RISCVException riscv_csrrw(CPURISCVState *env, int csrno, > target_ulong *ret_value, > target_ulong new_value, target_ulong write_ma= sk) > { > - RISCVException ret =3D riscv_csrrw_check(env, csrno, write_mask); > + RISCVException ret =3D riscv_csrrw_check(env, csrno, true); > if (ret !=3D RISCV_EXCP_NONE) { > return ret; > } > @@ -4473,13 +4484,45 @@ static RISCVException riscv_csrrw_do128(CPURISCVS= tate *env, int csrno, > return RISCV_EXCP_NONE; > } > > +RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, > + Int128 *ret_value) > +{ > + RISCVException ret; > + > + ret =3D riscv_csrrw_check(env, csrno, false); > + if (ret !=3D RISCV_EXCP_NONE) { > + return ret; > + } > + > + if (csr_ops[csrno].read128) { > + return riscv_csrrw_do128(env, csrno, ret_value, > + int128_zero(), int128_zero()); > + } > + > + /* > + * Fall back to 64-bit version for now, if the 128-bit alternative i= sn't > + * at all defined. > + * Note, some CSRs don't need to extend to MXLEN (64 upper bits non > + * significant), for those, this fallback is correctly handling the > + * accesses > + */ > + target_ulong old_value; > + ret =3D riscv_csrrw_do64(env, csrno, &old_value, > + (target_ulong)0, > + (target_ulong)0); > + if (ret =3D=3D RISCV_EXCP_NONE && ret_value) { > + *ret_value =3D int128_make64(old_value); > + } > + return ret; > +} > + > RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, > Int128 *ret_value, > Int128 new_value, Int128 write_mask) > { > RISCVException ret; > > - ret =3D riscv_csrrw_check(env, csrno, int128_nz(write_mask)); > + ret =3D riscv_csrrw_check(env, csrno, true); > if (ret !=3D RISCV_EXCP_NONE) { > return ret; > } > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index f414aaebdb..b95d47e9ac 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -51,7 +51,7 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) > } > > target_ulong val =3D 0; > - RISCVException ret =3D riscv_csrrw(env, csr, &val, 0, 0); > + RISCVException ret =3D riscv_csrr(env, csr, &val); > > if (ret !=3D RISCV_EXCP_NONE) { > riscv_raise_exception(env, ret, GETPC()); > @@ -84,9 +84,7 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr, > target_ulong helper_csrr_i128(CPURISCVState *env, int csr) > { > Int128 rv =3D int128_zero(); > - RISCVException ret =3D riscv_csrrw_i128(env, csr, &rv, > - int128_zero(), > - int128_zero()); > + RISCVException ret =3D riscv_csrr_i128(env, csr, &rv); > > if (ret !=3D RISCV_EXCP_NONE) { > riscv_raise_exception(env, ret, GETPC()); > -- > 2.34.1 > > CONFIDENTIALITY NOTICE: This e-mail (and its attachments) may contain confidential and legally priv= ileged information or information protected from disclosure. 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