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charset="utf-8" This is a ping to the patch below. https://lore.kernel.org/qemu-devel/TY0PR0101MB42850337F8917D1F514107FBA4D52= @TY0PR0101MB4285.apcprd01.prod.exchangelabs.com/ ________________________________ =E5=B7=AE=E5=87=BA=E4=BA=BA: TaiseiIto =E9=80=81=E4=BF=A1=E6=97=A5=E6=99=82: 2024=E5=B9=B46=E6=9C=8825=E6=97=A5 21= :03 =E5=AE=9B=E5=85=88: qemu-devel@nongnu.org CC: pbonzini@redhat.com ; mst@redhat.com ; TaiseiIto =E4=BB=B6=E5=90=8D: [PATCH] hw/intc/ioapic: Delete a wrong IRQ redirection = on I/O APIC Before this commit, interruptions from i8254 which should be sent to IRQ0 were sent to IRQ2. After this commit, these are correctly sent to IRQ0. When I had an HPET timer generate interruptions once per second to test an HPET driver in my operating system on QEMU, I observed more frequent interruptions than I configured on the HPET timer. I investigated the cause and found that not only interruptions from HPET but also interruptions from i8254 were sent to IRQ2 because of a redirection from IRQ0 to IRQ2. This redirection is added in hw/apic.c at commit 16b29ae1807b024bd5052301550f5d47dae958a2 but this redirection caused wrong interruptions. So I deleted the redirection. Finally, I confirmed there is no problem on 'make check' results and that interruptions from i8254 and interruptions from HPET are correclty sent to IRQ0 and IRQ2 respectively. Signed-off-by: TaiseiIto --- hw/intc/ioapic.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index 716ffc8bbb..6b630b45ca 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -154,15 +154,8 @@ static void ioapic_set_irq(void *opaque, int vector, i= nt level) { IOAPICCommonState *s =3D opaque; - /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps - * to GSI 2. GSI maps to ioapic 1-1. This is not - * the cleanest way of doing it but it should work. */ - trace_ioapic_set_irq(vector, level); ioapic_stat_update_irq(s, vector, level); - if (vector =3D=3D 0) { - vector =3D 2; - } if (vector < IOAPIC_NUM_PINS) { uint32_t mask =3D 1 << vector; uint64_t entry =3D s->ioredtbl[vector]; -- 2.34.1 --_000_SEZPR01MB43019C6C7D242A7A18B9C0B6A4DF2SEZPR01MB4301apcp_ Content-Type: text/html; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable
This is a ping to the patch below.
https://lore.kernel.= org/qemu-devel/TY0PR0101MB42850337F8917D1F514107FBA4D52@TY0PR0101MB4285.apc= prd01.prod.exchangelabs.com/

=1B$B:9=3DP?M=1B(B: TaiseiIto <taisei1212@outlook.jp>
=1B$BAw?.F|;~=1B(B: 2024=1B$BG/=1B(B6=1B$B7n=1B(B25=1B$BF|=1B(B= 21:03
=1B$B08@h=1B(B: qemu-devel@nongnu.org <qemu-devel@nongnu.org= >
CC: pbonzini@redhat.com <pbonzini@redhat.com>; mst@redhat= .com <mst@redhat.com>; TaiseiIto <taisei1212@outlook.jp>
=1B$B7oL>=1B(B: [PATCH] hw/intc/ioapic: Delete a wrong IRQ redi= rection on I/O APIC
 
Before this commit, interruptions from i825= 4 which should be sent to IRQ0
were sent to IRQ2. After this commit, these are correctly sent to IRQ0. Whe= n
I had an HPET timer generate interruptions once per second to test an HPET<= br> driver in my operating system on QEMU, I observed more frequent
interruptions than I configured on the HPET timer. I investigated the cause=
and found that not only interruptions from HPET but also interruptions from=
i8254 were sent to IRQ2 because of a redirection from IRQ0 to IRQ2. This redirection is added in hw/apic.c at commit
16b29ae1807b024bd5052301550f5d47dae958a2 but this redirection caused wrong<= br> interruptions. So I deleted the redirection. Finally, I confirmed there is<= br> no problem on 'make check' results and that interruptions from i8254 and interruptions from HPET are correclty sent to IRQ0 and IRQ2 respectively.
Signed-off-by: TaiseiIto <taisei1212@outlook.jp>
---
 hw/intc/ioapic.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index 716ffc8bbb..6b630b45ca 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -154,15 +154,8 @@ static void ioapic_set_irq(void *opaque, int vector, i= nt level)
 {
     IOAPICCommonState *s =3D opaque;
 
-    /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps -     * to GSI 2.  GSI maps to ioapic 1-1.  T= his is not
-     * the cleanest way of doing it but it should work= . */
-
     trace_ioapic_set_irq(vector, level);
     ioapic_stat_update_irq(s, vector, level);
-    if (vector =3D=3D 0) {
-        vector =3D 2;
-    }
     if (vector < IOAPIC_NUM_PINS) {
         uint32_t mask =3D 1 <&l= t; vector;
         uint64_t entry =3D s->i= oredtbl[vector];
--
2.34.1

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