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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a01:111:f400:fe5a::818; envelope-from=gihun.nam@outlook.com; helo=NAM12-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_06_12=1.543, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @outlook.com) X-ZM-MESSAGEID: 1701090189490000003 Content-Type: text/plain; charset="utf-8" The current implementation initializes the stack pointer of AVR devices to 0. Although older AVR devices used to be like that, newer ones set it to RAMEND. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1525 Signed-off-by: Gihun Nam Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Edit code to use QOM property and add more description to commit message about the changes Thanks for the detailed help, Mr. Peter! P.S. I don't understand how replies work with git send-email, so if I've done something wrong, please bear with me. hw/avr/atmega.c | 4 ++++ target/avr/cpu.c | 10 +++++++++- target/avr/cpu.h | 3 +++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index a34803e642..31c8992d75 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -233,6 +233,10 @@ static void atmega_realize(DeviceState *dev, Error **e= rrp) =20 /* CPU */ object_initialize_child(OBJECT(dev), "cpu", &s->cpu, mc->cpu_type); + + object_property_set_uint(OBJECT(&s->cpu), "init-sp", + mc->io_size + mc->sram_size - 1, &error_abort= ); + qdev_realize(DEVICE(&s->cpu), NULL, &error_abort); cpudev =3D DEVICE(&s->cpu); =20 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 44de1e18d1..999c010ded 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -25,6 +25,7 @@ #include "cpu.h" #include "disas/dis-asm.h" #include "tcg/debug-assert.h" +#include "hw/qdev-properties.h" =20 static void avr_cpu_set_pc(CPUState *cs, vaddr value) { @@ -95,7 +96,7 @@ static void avr_cpu_reset_hold(Object *obj) env->rampY =3D 0; env->rampZ =3D 0; env->eind =3D 0; - env->sp =3D 0; + env->sp =3D cpu->init_sp; =20 env->skip =3D 0; =20 @@ -152,6 +153,11 @@ static void avr_cpu_initfn(Object *obj) sizeof(cpu->env.intsrc) * 8); } =20 +static Property avr_cpu_properties[] =3D { + DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0), + DEFINE_PROP_END_OF_LIST() +}; + static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; @@ -228,6 +234,8 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) =20 device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_re= alize); =20 + device_class_set_props(dc, avr_cpu_properties); + resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL, &mcc->parent_phases); =20 diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 8a17862737..7960c5c57a 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -145,6 +145,9 @@ struct ArchCPU { CPUState parent_obj; =20 CPUAVRState env; + + /* Initial value of stack pointer */ + uint32_t init_sp; }; =20 /** --=20 2.39.2