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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=40.92.4.40; envelope-from=heecheol.yang@outlook.com; helo=NAM02-CY1-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/03 07:47:29 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "S.E.Harris@kent.ac.uk" , "mrolnik@gmail.com" , Hee-cheol Yang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @outlook.com) --_000_DM6PR16MB2473974517176215E9519911E60E0DM6PR16MB2473namp_ Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" I am very sorry for your inconvenience. This is 3rd version of the patch fo= r what I did. I should have read the contribution guide again and again. I am very sorry = again. The contents of the patch is the same with the v2. This mail is just for pa= tchew and making a new thread. Here are what I changed from the v1: * Remove unnecessary header inclusions * Replace codes for unreachable conditions with g_assert_not_reached() = function * Remove 'enable' field from AVRGPIOState structure: It is actually unn= ecessary. I copied this field from AVRUSARTState structure. Thanks a lot! With best regards Heecheol Yang. Add some of these features for avr gpio: - GPIO I/O : PORTx registers - Data Direction : DDRx registers Following things are not supported yet: - PINx registers - MCUR registers - Even though read/write for DDRx registers are implemented, actual direction controls are not supported yet. Signed-off-by: Heecheol Yang --- hw/avr/Kconfig | 1 + hw/avr/atmega.c | 7 ++- hw/avr/atmega.h | 2 + hw/gpio/Kconfig | 3 + hw/gpio/avr_gpio.c | 112 +++++++++++++++++++++++++++++++++++++ hw/gpio/meson.build | 2 + include/hw/gpio/avr_gpio.h | 46 +++++++++++++++ 7 files changed, 171 insertions(+), 2 deletions(-) create mode 100644 hw/gpio/avr_gpio.c create mode 100644 include/hw/gpio/avr_gpio.h diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig index d31298c3cc..16a57ced11 100644 --- a/hw/avr/Kconfig +++ b/hw/avr/Kconfig @@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU select AVR_TIMER16 select AVR_USART select AVR_POWER + select AVR_GPIO config ARDUINO select AVR_ATMEGA_MCU diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 44c6afebbb..ad942028fd 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -283,8 +283,11 @@ static void atmega_realize(DeviceState *dev, Error **e= rrp) continue; } devname =3D g_strdup_printf("atmega-gpio-%c", 'a' + (char)i); - create_unimplemented_device(devname, - OFFSET_DATA + mc->dev[idx].addr, 3); + object_initialize_child(OBJECT(dev), devname, &s->gpio[i], + TYPE_AVR_GPIO); + sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, + OFFSET_DATA + mc->dev[idx].addr); g_free(devname); } diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h index a99ee15c7e..e2289d5744 100644 --- a/hw/avr/atmega.h +++ b/hw/avr/atmega.h @@ -13,6 +13,7 @@ #include "hw/char/avr_usart.h" #include "hw/timer/avr_timer16.h" +#include "hw/gpio/avr_gpio.h" #include "hw/misc/avr_power.h" #include "target/avr/cpu.h" #include "qom/object.h" @@ -44,6 +45,7 @@ struct AtmegaMcuState { DeviceState *io; AVRMaskState pwr[POWER_MAX]; AVRUsartState usart[USART_MAX]; + AVRGPIOState gpio[GPIO_MAX]; AVRTimer16State timer[TIMER_MAX]; uint64_t xtal_freq_hz; }; diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index b6fdaa2586..1752d0ce56 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -10,3 +10,6 @@ config GPIO_KEY config SIFIVE_GPIO bool + +config AVR_GPIO + bool diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c new file mode 100644 index 0000000000..6ca8e8703a --- /dev/null +++ b/hw/gpio/avr_gpio.c @@ -0,0 +1,112 @@ +/* + * AVR processors GPIO registers emulation. + * + * Copyright (C) 2020 Heecheol Yang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/gpio/avr_gpio.h" +#include "hw/qdev-properties.h" + +static void avr_gpio_reset(DeviceState *dev) +{ + AVRGPIOState *gpio =3D AVR_GPIO(dev); + gpio->ddr_val =3D 0u; + gpio->port_val =3D 0u; +} +static uint64_t avr_gpio_read(void *opaque, hwaddr offset, unsigned int si= ze) +{ + AVRGPIOState *s =3D (AVRGPIOState *)opaque; + switch (offset) { + case GPIO_PIN: + /* Not implemented yet */ + break; + case GPIO_DDR: + return s->ddr_val; + break; + case GPIO_PORT: + return s->port_val; + default: + g_assert_not_reached(); + break; + } + return 0; +} + +static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t value, + unsigned int size) +{ + AVRGPIOState *s =3D (AVRGPIOState *)opaque; + switch (offset) { + case GPIO_PIN: + /* Not implemented yet */ + break; + case GPIO_DDR: + s->ddr_val =3D value & 0xF; + break; + case GPIO_PORT: + s->port_val =3D value & 0xF; + break; + default: + g_assert_not_reached(); + break; + } +} + +static const MemoryRegionOps avr_gpio_ops =3D { + .read =3D avr_gpio_read, + .write =3D avr_gpio_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void avr_gpio_init(Object *obj) +{ + AVRGPIOState *s =3D AVR_GPIO(obj); + memory_region_init_io(&s->mmio, obj, &avr_gpio_ops, s, TYPE_AVR_GPIO, = 3); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} +static void avr_gpio_realize(DeviceState *dev, Error **errp) +{ + avr_gpio_reset(dev); +} + + +static void avr_gpio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D avr_gpio_reset; + dc->realize =3D avr_gpio_realize; +} + +static const TypeInfo avr_gpio_info =3D { + .name =3D TYPE_AVR_GPIO, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AVRGPIOState), + .instance_init =3D avr_gpio_init, + .class_init =3D avr_gpio_class_init, +}; + +static void avr_gpio_register_types(void) +{ + type_register_static(&avr_gpio_info); +} + +type_init(avr_gpio_register_types) diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 86cae9a0f3..258bd5dcfc 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -11,3 +11,5 @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_= gpio.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) + +softmmu_ss.add(when: 'CONFIG_AVR_GPIO', if_true: files('avr_gpio.c')) diff --git a/include/hw/gpio/avr_gpio.h b/include/hw/gpio/avr_gpio.h new file mode 100644 index 0000000000..84d783f8fc --- /dev/null +++ b/include/hw/gpio/avr_gpio.h @@ -0,0 +1,46 @@ +/* + * AVR processors GPIO registers definition. + * + * Copyright (C) 2020 Heecheol Yang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef AVR_GPIO_H +#define AVR_GPIO_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +/* Offsets of registers. */ +#define GPIO_PIN 0x00 +#define GPIO_DDR 0x01 +#define GPIO_PORT 0x02 + +#define TYPE_AVR_GPIO "avr-gpio" +OBJECT_DECLARE_SIMPLE_TYPE(AVRGPIOState, AVR_GPIO) + +struct AVRGPIOState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + + uint8_t ddr_val; + uint8_t port_val; + +}; + +#endif /* AVR_GPIO_H */ -- 2.17.1 --_000_DM6PR16MB2473974517176215E9519911E60E0DM6PR16MB2473namp_ Content-Type: text/html; charset="ks_c_5601-1987" Content-Transfer-Encoding: quoted-printable
I am very sorry for your inconvenience. This is 3rd version of the patch fo= r what I did. 
I should have read the contribution guide again and again. I am very sorry = again.

The contents of the patch is the same with the v2. This mail is just for pa= tchew and making a new thread.
Here are what I changed from the v1:
  • Remove unnecessary header inclusions
  • Replace codes for unreacha= ble conditions with g_assert_not_reached() function
  • Remove 'enable'= field from AVRGPIOState structure: It is actually unnecessary. I copied th= is field from AVRUSARTState structure.

Thanks a lot!
With best regards
Heecheol Yang.

Add some of these features for avr gpio:

  - GPIO I/O : PORTx registers
  - Data Direction : DDRx registers

Following things are not supported yet:
  - PINx registers
  - MCUR registers
  - Even though read/write for DDRx registers are
    implemented, actual direction controls are not
    supported yet.

Signed-off-by: Heecheol Yang <heecheol.yang@outlook.com>
---
 hw/avr/Kconfig         &= nbsp;   |   1 +
 hw/avr/atmega.c         =    |   7 ++-
 hw/avr/atmega.h         =    |   2 +
 hw/gpio/Kconfig         =    |   3 +
 hw/gpio/avr_gpio.c         | = 112 +++++++++++++++++++++++++++++++++++++
 hw/gpio/meson.build        | =   2 +
 include/hw/gpio/avr_gpio.h |  46 +++++++++++++++
 7 files changed, 171 insertions(+), 2 deletions(-)
 create mode 100644 hw/gpio/avr_gpio.c
 create mode 100644 include/hw/gpio/avr_gpio.h

diff --git a/hw/avr/Kconfig b/hw/avr/Kconfig
index d31298c3cc..16a57ced11 100644
--- a/hw/avr/Kconfig
+++ b/hw/avr/Kconfig
@@ -3,6 +3,7 @@ config AVR_ATMEGA_MCU
     select AVR_TIMER16
     select AVR_USART
     select AVR_POWER
+    select AVR_GPIO
 
 config ARDUINO
     select AVR_ATMEGA_MCU
diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c
index 44c6afebbb..ad942028fd 100644
--- a/hw/avr/atmega.c
+++ b/hw/avr/atmega.c
@@ -283,8 +283,11 @@ static void atmega_realize(DeviceState *dev, Error **e= rrp)
             co= ntinue;
         }
         devname =3D g_strdup_print= f("atmega-gpio-%c", 'a' + (char)i);
-        create_unimplemented_device(dev= name,
-            &n= bsp;            = ;           OFFSET_DATA += mc->dev[idx].addr, 3);
+        object_initialize_child(OBJECT(= dev), devname, &s->gpio[i],
+            &n= bsp;            = ;       TYPE_AVR_GPIO);
+        sysbus_realize(SYS_BUS_DEVICE(&= amp;s->gpio[i]), &error_abort);
+        sysbus_mmio_map(SYS_BUS_DEVICE(= &s->gpio[i]), 0,
+            OFFSET_= DATA + mc->dev[idx].addr);
         g_free(devname);
     }
 
diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
index a99ee15c7e..e2289d5744 100644
--- a/hw/avr/atmega.h
+++ b/hw/avr/atmega.h
@@ -13,6 +13,7 @@
 
 #include "hw/char/avr_usart.h"
 #include "hw/timer/avr_timer16.h"
+#include "hw/gpio/avr_gpio.h"
 #include "hw/misc/avr_power.h"
 #include "target/avr/cpu.h"
 #include "qom/object.h"
@@ -44,6 +45,7 @@ struct AtmegaMcuState {
     DeviceState *io;
     AVRMaskState pwr[POWER_MAX];
     AVRUsartState usart[USART_MAX];
+    AVRGPIOState gpio[GPIO_MAX];
     AVRTimer16State timer[TIMER_MAX];
     uint64_t xtal_freq_hz;
 };
diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig
index b6fdaa2586..1752d0ce56 100644
--- a/hw/gpio/Kconfig
+++ b/hw/gpio/Kconfig
@@ -10,3 +10,6 @@ config GPIO_KEY
 
 config SIFIVE_GPIO
     bool
+
+config AVR_GPIO
+    bool
diff --git a/hw/gpio/avr_gpio.c b/hw/gpio/avr_gpio.c
new file mode 100644
index 0000000000..6ca8e8703a
--- /dev/null
+++ b/hw/gpio/avr_gpio.c
@@ -0,0 +1,112 @@
+/*
+ * AVR processors GPIO registers emulation.
+ *
+ * Copyright (C) 2020 Heecheol Yang <heecheol.yang@outlook.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along=
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "hw/sysbus.h"
+#include "hw/irq.h"
+#include "hw/gpio/avr_gpio.h"
+#include "hw/qdev-properties.h"
+
+static void avr_gpio_reset(DeviceState *dev)
+{
+    AVRGPIOState *gpio =3D AVR_GPIO(dev);
+    gpio->ddr_val =3D 0u;
+    gpio->port_val =3D 0u;
+}
+static uint64_t avr_gpio_read(void *opaque, hwaddr offset, unsigned int si= ze)
+{
+    AVRGPIOState *s =3D (AVRGPIOState *)opaque;
+    switch (offset) {
+    case GPIO_PIN:
+        /* Not implemented yet */
+        break;
+    case GPIO_DDR:
+        return s->ddr_val;
+        break;
+    case GPIO_PORT:
+        return s->port_val;
+    default:
+        g_assert_not_reached();
+        break;
+    }
+    return 0;
+}
+
+static void avr_gpio_write(void *opaque, hwaddr offset, uint64_t value, +            &n= bsp;            = ;       unsigned int size)
+{
+    AVRGPIOState *s =3D (AVRGPIOState *)opaque;
+    switch (offset) {
+    case GPIO_PIN:
+        /* Not implemented yet */
+        break;
+    case GPIO_DDR:
+        s->ddr_val =3D value & 0= xF;
+        break;
+    case GPIO_PORT:
+        s->port_val =3D value & = 0xF;
+        break;
+    default:
+        g_assert_not_reached();
+        break;
+    }
+}
+
+static const MemoryRegionOps avr_gpio_ops =3D {
+    .read =3D avr_gpio_read,
+    .write =3D avr_gpio_write,
+    .endianness =3D DEVICE_NATIVE_ENDIAN,
+};
+
+static void avr_gpio_init(Object *obj)
+{
+    AVRGPIOState *s =3D AVR_GPIO(obj);
+    memory_region_init_io(&s->mmio, obj, &avr_gp= io_ops, s, TYPE_AVR_GPIO, 3);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);=
+}
+static void avr_gpio_realize(DeviceState *dev, Error **errp)
+{
+    avr_gpio_reset(dev);
+}
+
+
+static void avr_gpio_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+    dc->reset =3D avr_gpio_reset;
+    dc->realize =3D avr_gpio_realize;
+}
+
+static const TypeInfo avr_gpio_info =3D {
+    .name        &n= bsp; =3D TYPE_AVR_GPIO,
+    .parent        =3D T= YPE_SYS_BUS_DEVICE,
+    .instance_size =3D sizeof(AVRGPIOState),
+    .instance_init =3D avr_gpio_init,
+    .class_init    =3D avr_gpio_class_init,<= br> +};
+
+static void avr_gpio_register_types(void)
+{
+    type_register_static(&avr_gpio_info);
+}
+
+type_init(avr_gpio_register_types)
diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build
index 86cae9a0f3..258bd5dcfc 100644
--- a/hw/gpio/meson.build
+++ b/hw/gpio/meson.build
@@ -11,3 +11,5 @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_= gpio.c'))
 softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c')= )
 softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio= .c'))
 softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpi= o.c'))
+
+softmmu_ss.add(when: 'CONFIG_AVR_GPIO', if_true: files('avr_gpio.c'))
diff --git a/include/hw/gpio/avr_gpio.h b/include/hw/gpio/avr_gpio.h
new file mode 100644
index 0000000000..84d783f8fc
--- /dev/null
+++ b/include/hw/gpio/avr_gpio.h
@@ -0,0 +1,46 @@
+/*
+ * AVR processors GPIO registers definition.
+ *
+ * Copyright (C) 2020 Heecheol Yang <heecheol.yang@outlook.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along=
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef AVR_GPIO_H
+#define AVR_GPIO_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+/* Offsets of registers. */
+#define GPIO_PIN   0x00
+#define GPIO_DDR   0x01
+#define GPIO_PORT  0x02
+
+#define TYPE_AVR_GPIO "avr-gpio"
+OBJECT_DECLARE_SIMPLE_TYPE(AVRGPIOState, AVR_GPIO)
+
+struct AVRGPIOState {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    MemoryRegion mmio;
+
+    uint8_t ddr_val;
+    uint8_t port_val;
+
+};
+
+#endif /* AVR_GPIO_H */
--
2.17.1

--_000_DM6PR16MB2473974517176215E9519911E60E0DM6PR16MB2473namp_--