From nobody Fri Nov 7 02:16:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546035920195300.3419594410241; Fri, 28 Dec 2018 14:25:20 -0800 (PST) Received: from localhost ([127.0.0.1]:33533 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gd0ZC-0002A3-JQ for importer@patchew.org; Fri, 28 Dec 2018 17:25:18 -0500 Received: from eggs.gnu.org ([208.118.235.92]:48355) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gd0U0-00050Z-M1 for qemu-devel@nongnu.org; Fri, 28 Dec 2018 17:20:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gd0I6-0005vs-7Q for qemu-devel@nongnu.org; Fri, 28 Dec 2018 17:07:41 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:40169) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gd0I4-0005uU-Kg for qemu-devel@nongnu.org; Fri, 28 Dec 2018 17:07:36 -0500 Received: by mail-pg1-x541.google.com with SMTP id z10so10517105pgp.7 for ; Fri, 28 Dec 2018 14:07:36 -0800 (PST) Received: from rohan.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id c13sm89361780pfe.93.2018.12.28.14.07.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 28 Dec 2018 14:07:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=34pV6twaYRY22dnKmtdlxN/IwYgUcz33+iJ7bcLTxw0=; b=TwdNqd1jfpxMoCHJ2FsEQUabLdhzNbaQFUJD6oX3DoKnHoImQ1tXZwSXSdZL21PLFe gzGBZ3k/RlR87Td42TxyEJJjBuDzO3YvHWxCsNXKKwRsT3YpccUs20tJCDLe2IKciK5H /MYsoj1vsPwye1VntDYGsKMP8F4mpF2TMD8YXlbNrYrBB4UK/MQgJ6S1W1qA2UjTMiSK UZ9EnEcKxVMIPC90RXt+PNFL84WUwNBmk5Ka8qmNEzI5z4czckgJXvarcsTiBZHN5EqM jnKS7qkH6k2mTODEZ4AHzVKQg3HrDR0b9fE98/yDCgAwqbsJyGm6ZzWk0G3fzPm/YOjf FF6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=34pV6twaYRY22dnKmtdlxN/IwYgUcz33+iJ7bcLTxw0=; b=ZqOjsDTp34prmNlVoWu35sRHX73A60XpaqMGfxcqpftFGG/s4z7/20gFUUd7Tbazjt 0YctNYgS3gVshNUIVdwvNBbdLCvzowcDBZTZfW5/8pHubjBbPaGpS6i67UFtgLRSAFZE UEHnQTALs3CrAesRcL8P61BqKOrmLnAhsUoJuBtLvOFhZueXkBqgJmRQ/LrNyS9LSNeJ E33I1rPRjp6KgudGWuwHgTIsIGJS12mW1OO7ve1AYs/gL1LRO7nJiVY84nFlVvjrpJHo 9ia6Fo2MxpcvfQAHmR9VTtQt4v+Apr/hIyTHbTcjWp5wm80nBHFZwDhR6QIPPF8H2Ra+ 3xIg== X-Gm-Message-State: AA+aEWZf5JNtM67FHLjMgKty+jKSK1aF3M6ELAfTe8kj3HLz25M2ucEp VPbyz/r5fO43LjdXFAQdepOiPsLsjrt8ww== X-Google-Smtp-Source: AFSGD/U3xISSTflaoGsiqtW1rB4sFxXCSkjS5Y/FR/F75LmA/bq7TKs3X73XimoIdubEXOMhcCpRLg== X-Received: by 2002:a62:1a91:: with SMTP id a139mr30636654pfa.64.1546034854607; Fri, 28 Dec 2018 14:07:34 -0800 (PST) From: Jim Wilson To: qemu-devel@nongnu.org Date: Fri, 28 Dec 2018 14:07:31 -0800 Message-Id: <20181228220731.4753-1-jimw@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 1/5 v2] RISC-V: Add 32-bit gdb xml files. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Jim Wilson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Jim Wilson Acked-by: Alistair Francis --- configure | 1 + gdb-xml/riscv-32bit-cpu.xml | 43 ++++++++ gdb-xml/riscv-32bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++= ++++ gdb-xml/riscv-32bit-fpu.xml | 46 ++++++++ 4 files changed, 340 insertions(+) create mode 100644 gdb-xml/riscv-32bit-cpu.xml create mode 100644 gdb-xml/riscv-32bit-csr.xml create mode 100644 gdb-xml/riscv-32bit-fpu.xml diff --git a/configure b/configure index 224d307..4e05eed 100755 --- a/configure +++ b/configure @@ -7208,6 +7208,7 @@ case "$target_name" in TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv mttcg=3Dyes + gdb_xml_files=3D"riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-c= sr.xml" target_compiler=3D$cross_cc_riscv32 ;; riscv64) diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml new file mode 100644 index 0000000..c02f86c --- /dev/null +++ b/gdb-xml/riscv-32bit-cpu.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-32bit-csr.xml b/gdb-xml/riscv-32bit-csr.xml new file mode 100644 index 0000000..4aea9e6 --- /dev/null +++ b/gdb-xml/riscv-32bit-csr.xml @@ -0,0 +1,250 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-32bit-fpu.xml b/gdb-xml/riscv-32bit-fpu.xml new file mode 100644 index 0000000..783287d --- /dev/null +++ b/gdb-xml/riscv-32bit-fpu.xml @@ -0,0 +1,46 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --=20 2.7.4 From nobody Fri Nov 7 02:16:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 2/5 v2] RISC-V: Add 64-bit gdb xml files. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Jim Wilson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Jim Wilson Acked-by: Alistair Francis --- configure | 1 + gdb-xml/riscv-64bit-cpu.xml | 43 ++++++++ gdb-xml/riscv-64bit-csr.xml | 250 ++++++++++++++++++++++++++++++++++++++++= ++++ gdb-xml/riscv-64bit-fpu.xml | 52 +++++++++ 4 files changed, 346 insertions(+) create mode 100644 gdb-xml/riscv-64bit-cpu.xml create mode 100644 gdb-xml/riscv-64bit-csr.xml create mode 100644 gdb-xml/riscv-64bit-fpu.xml diff --git a/configure b/configure index 4e05eed..00b7495 100755 --- a/configure +++ b/configure @@ -7215,6 +7215,7 @@ case "$target_name" in TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv mttcg=3Dyes + gdb_xml_files=3D"riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-c= sr.xml" target_compiler=3D$cross_cc_riscv64 ;; sh4|sh4eb) diff --git a/gdb-xml/riscv-64bit-cpu.xml b/gdb-xml/riscv-64bit-cpu.xml new file mode 100644 index 0000000..f37d7f3 --- /dev/null +++ b/gdb-xml/riscv-64bit-cpu.xml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-csr.xml b/gdb-xml/riscv-64bit-csr.xml new file mode 100644 index 0000000..a3de834 --- /dev/null +++ b/gdb-xml/riscv-64bit-csr.xml @@ -0,0 +1,250 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/riscv-64bit-fpu.xml b/gdb-xml/riscv-64bit-fpu.xml new file mode 100644 index 0000000..fb24b72 --- /dev/null +++ b/gdb-xml/riscv-64bit-fpu.xml @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + --=20 2.7.4 From nobody Fri Nov 7 02:16:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 3/5 v2] RISC-V: Map gdb CSR reg numbers to hw reg numbers. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Jim Wilson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The gdb CSR xml file has registers in documentation order, not numerical order, so we need a table to map the register numbers. This also adds some missing CSR_* register macros. Signed-off-by: Jim Wilson --- target/riscv/cpu_bits.h | 35 ++++++- target/riscv/csr-map.h | 248 ++++++++++++++++++++++++++++++++++++++++++++= ++++ target/riscv/gdbstub.c | 1 + 3 files changed, 282 insertions(+), 2 deletions(-) create mode 100644 target/riscv/csr-map.h diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 5439f47..316d500 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -135,16 +135,22 @@ /* Legacy Counter Setup (priv v1.9.1) */ #define CSR_MUCOUNTEREN 0x320 #define CSR_MSCOUNTEREN 0x321 +#define CSR_MHCOUNTEREN 0x322 =20 /* Machine Trap Handling */ #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 +#define CSR_MTVAL 0x343 #define CSR_MIP 0x344 =20 +/* Legacy Machine Trap Handling (priv v1.9.1) */ +#define CSR_MBADADDR 0x343 + /* Supervisor Trap Setup */ #define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 #define CSR_SIE 0x104 #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 @@ -153,9 +159,12 @@ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 +#define CSR_STVAL 0x143 #define CSR_SIP 0x144 =20 +/* Legacy Supervisor Trap Handling (priv v1.9.1) */ +#define CSR_SBADADDR 0x143 + /* Supervisor Protection and Translation */ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 @@ -282,6 +291,28 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f =20 +/* Legacy Hypervisor Trap Setup (priv v1.9.1) */ +#define CSR_HSTATUS 0x200 +#define CSR_HEDELEG 0x202 +#define CSR_HIDELEG 0x203 +#define CSR_HIE 0x204 +#define CSR_HTVEC 0x205 + +/* Legacy Hypervisor Trap Handling (priv v1.9.1) */ +#define CSR_HSCRATCH 0x240 +#define CSR_HEPC 0x241 +#define CSR_HCAUSE 0x242 +#define CSR_HBADADDR 0x243 +#define CSR_HIP 0x244 + +/* Legacy Machine Protection and Translation (priv v1.9.1) */ +#define CSR_MBASE 0x380 +#define CSR_MBOUND 0x381 +#define CSR_MIBASE 0x382 +#define CSR_MIBOUND 0x383 +#define CSR_MDBASE 0x384 +#define CSR_MDBOUND 0x385 + /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 diff --git a/target/riscv/csr-map.h b/target/riscv/csr-map.h new file mode 100644 index 0000000..cce32fd --- /dev/null +++ b/target/riscv/csr-map.h @@ -0,0 +1,248 @@ +/* + * The GDB CSR xml files list them in documentation order, not numerical o= rder, + * and are missing entries for unnamed CSRs. So we need to map the gdb nu= mbers + * to the hardware numbers. + */ + +int csr_register_map[] =3D { + CSR_USTATUS, + CSR_UIE, + CSR_UTVEC, + CSR_USCRATCH, + CSR_UEPC, + CSR_UCAUSE, + CSR_UTVAL, + CSR_UIP, + CSR_FFLAGS, + CSR_FRM, + CSR_FCSR, + CSR_CYCLE, + CSR_TIME, + CSR_INSTRET, + CSR_HPMCOUNTER3, + CSR_HPMCOUNTER4, + CSR_HPMCOUNTER5, + CSR_HPMCOUNTER6, + CSR_HPMCOUNTER7, + CSR_HPMCOUNTER8, + CSR_HPMCOUNTER9, + CSR_HPMCOUNTER10, + CSR_HPMCOUNTER11, + CSR_HPMCOUNTER12, + CSR_HPMCOUNTER13, + CSR_HPMCOUNTER14, + CSR_HPMCOUNTER15, + CSR_HPMCOUNTER16, + CSR_HPMCOUNTER17, + CSR_HPMCOUNTER18, + CSR_HPMCOUNTER19, + CSR_HPMCOUNTER20, + CSR_HPMCOUNTER21, + CSR_HPMCOUNTER22, + CSR_HPMCOUNTER23, + CSR_HPMCOUNTER24, + CSR_HPMCOUNTER25, + CSR_HPMCOUNTER26, + CSR_HPMCOUNTER27, + CSR_HPMCOUNTER28, + CSR_HPMCOUNTER29, + CSR_HPMCOUNTER30, + CSR_HPMCOUNTER31, + CSR_CYCLEH, + CSR_TIMEH, + CSR_INSTRETH, + CSR_HPMCOUNTER3H, + CSR_HPMCOUNTER4H, + CSR_HPMCOUNTER5H, + CSR_HPMCOUNTER6H, + CSR_HPMCOUNTER7H, + CSR_HPMCOUNTER8H, + CSR_HPMCOUNTER9H, + CSR_HPMCOUNTER10H, + CSR_HPMCOUNTER11H, + CSR_HPMCOUNTER12H, + CSR_HPMCOUNTER13H, + CSR_HPMCOUNTER14H, + CSR_HPMCOUNTER15H, + CSR_HPMCOUNTER16H, + CSR_HPMCOUNTER17H, + CSR_HPMCOUNTER18H, + CSR_HPMCOUNTER19H, + CSR_HPMCOUNTER20H, + CSR_HPMCOUNTER21H, + CSR_HPMCOUNTER22H, + CSR_HPMCOUNTER23H, + CSR_HPMCOUNTER24H, + CSR_HPMCOUNTER25H, + CSR_HPMCOUNTER26H, + CSR_HPMCOUNTER27H, + CSR_HPMCOUNTER28H, + CSR_HPMCOUNTER29H, + CSR_HPMCOUNTER30H, + CSR_HPMCOUNTER31H, + CSR_SSTATUS, + CSR_SEDELEG, + CSR_SIDELEG, + CSR_SIE, + CSR_STVEC, + CSR_SCOUNTEREN, + CSR_SSCRATCH, + CSR_SEPC, + CSR_SCAUSE, + CSR_STVAL, + CSR_SIP, + CSR_SATP, + CSR_MVENDORID, + CSR_MARCHID, + CSR_MIMPID, + CSR_MHARTID, + CSR_MSTATUS, + CSR_MISA, + CSR_MEDELEG, + CSR_MIDELEG, + CSR_MIE, + CSR_MTVEC, + CSR_MCOUNTEREN, + CSR_MSCRATCH, + CSR_MEPC, + CSR_MCAUSE, + CSR_MTVAL, + CSR_MIP, + CSR_PMPCFG0, + CSR_PMPCFG1, + CSR_PMPCFG2, + CSR_PMPCFG3, + CSR_PMPADDR0, + CSR_PMPADDR1, + CSR_PMPADDR2, + CSR_PMPADDR3, + CSR_PMPADDR4, + CSR_PMPADDR5, + CSR_PMPADDR6, + CSR_PMPADDR7, + CSR_PMPADDR8, + CSR_PMPADDR9, + CSR_PMPADDR10, + CSR_PMPADDR11, + CSR_PMPADDR12, + CSR_PMPADDR13, + CSR_PMPADDR14, + CSR_PMPADDR15, + CSR_MCYCLE, + CSR_MINSTRET, + CSR_MHPMCOUNTER3, + CSR_MHPMCOUNTER4, + CSR_MHPMCOUNTER5, + CSR_MHPMCOUNTER6, + CSR_MHPMCOUNTER7, + CSR_MHPMCOUNTER8, + CSR_MHPMCOUNTER9, + CSR_MHPMCOUNTER10, + CSR_MHPMCOUNTER11, + CSR_MHPMCOUNTER12, + CSR_MHPMCOUNTER13, + CSR_MHPMCOUNTER14, + CSR_MHPMCOUNTER15, + CSR_MHPMCOUNTER16, + CSR_MHPMCOUNTER17, + CSR_MHPMCOUNTER18, + CSR_MHPMCOUNTER19, + CSR_MHPMCOUNTER20, + CSR_MHPMCOUNTER21, + CSR_MHPMCOUNTER22, + CSR_MHPMCOUNTER23, + CSR_MHPMCOUNTER24, + CSR_MHPMCOUNTER25, + CSR_MHPMCOUNTER26, + CSR_MHPMCOUNTER27, + CSR_MHPMCOUNTER28, + CSR_MHPMCOUNTER29, + CSR_MHPMCOUNTER30, + CSR_MHPMCOUNTER31, + CSR_MCYCLEH, + CSR_MINSTRETH, + CSR_MHPMCOUNTER3H, + CSR_MHPMCOUNTER4H, + CSR_MHPMCOUNTER5H, + CSR_MHPMCOUNTER6H, + CSR_MHPMCOUNTER7H, + CSR_MHPMCOUNTER8H, + CSR_MHPMCOUNTER9H, + CSR_MHPMCOUNTER10H, + CSR_MHPMCOUNTER11H, + CSR_MHPMCOUNTER12H, + CSR_MHPMCOUNTER13H, + CSR_MHPMCOUNTER14H, + CSR_MHPMCOUNTER15H, + CSR_MHPMCOUNTER16H, + CSR_MHPMCOUNTER17H, + CSR_MHPMCOUNTER18H, + CSR_MHPMCOUNTER19H, + CSR_MHPMCOUNTER20H, + CSR_MHPMCOUNTER21H, + CSR_MHPMCOUNTER22H, + CSR_MHPMCOUNTER23H, + CSR_MHPMCOUNTER24H, + CSR_MHPMCOUNTER25H, + CSR_MHPMCOUNTER26H, + CSR_MHPMCOUNTER27H, + CSR_MHPMCOUNTER28H, + CSR_MHPMCOUNTER29H, + CSR_MHPMCOUNTER30H, + CSR_MHPMCOUNTER31H, + CSR_MHPMEVENT3, + CSR_MHPMEVENT4, + CSR_MHPMEVENT5, + CSR_MHPMEVENT6, + CSR_MHPMEVENT7, + CSR_MHPMEVENT8, + CSR_MHPMEVENT9, + CSR_MHPMEVENT10, + CSR_MHPMEVENT11, + CSR_MHPMEVENT12, + CSR_MHPMEVENT13, + CSR_MHPMEVENT14, + CSR_MHPMEVENT15, + CSR_MHPMEVENT16, + CSR_MHPMEVENT17, + CSR_MHPMEVENT18, + CSR_MHPMEVENT19, + CSR_MHPMEVENT20, + CSR_MHPMEVENT21, + CSR_MHPMEVENT22, + CSR_MHPMEVENT23, + CSR_MHPMEVENT24, + CSR_MHPMEVENT25, + CSR_MHPMEVENT26, + CSR_MHPMEVENT27, + CSR_MHPMEVENT28, + CSR_MHPMEVENT29, + CSR_MHPMEVENT30, + CSR_MHPMEVENT31, + CSR_TSELECT, + CSR_TDATA1, + CSR_TDATA2, + CSR_TDATA3, + CSR_DCSR, + CSR_DPC, + CSR_DSCRATCH, + CSR_HSTATUS, + CSR_HEDELEG, + CSR_HIDELEG, + CSR_HIE, + CSR_HTVEC, + CSR_HSCRATCH, + CSR_HEPC, + CSR_HCAUSE, + CSR_HBADADDR, + CSR_HIP, + CSR_MBASE, + CSR_MBOUND, + CSR_MIBASE, + CSR_MIBOUND, + CSR_MDBASE, + CSR_MDBOUND, + CSR_MUCOUNTEREN, + CSR_MSCOUNTEREN, + CSR_MHCOUNTEREN, +}; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 4f919b6..71c3eb1 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -20,6 +20,7 @@ #include "qemu-common.h" #include "exec/gdbstub.h" #include "cpu.h" +#include "csr-map.h" =20 int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) { --=20 2.7.4 From nobody Fri Nov 7 02:16:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1546035861390155.16359093723952; Fri, 28 Dec 2018 14:24:21 -0800 (PST) Received: from localhost ([127.0.0.1]:33531 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gd0YG-0001LK-0M for importer@patchew.org; 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Fri, 28 Dec 2018 14:10:20 -0800 (PST) From: Jim Wilson To: qemu-devel@nongnu.org Date: Fri, 28 Dec 2018 14:10:18 -0800 Message-Id: <20181228221018.5022-1-jimw@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 4/5 v2] RISC-V: Add debug support for accessing CSRs. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Jim Wilson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Adds a debugger parameter to csr_read_helper and csr_write_helper. When this is true, we disable illegal instruction checks. Signed-off-by: Jim Wilson Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- linux-user/riscv/signal.c | 5 ++- target/riscv/cpu.h | 7 +++- target/riscv/cpu_helper.c | 4 +- target/riscv/gdbstub.c | 4 +- target/riscv/op_helper.c | 93 ++++++++++++++++++++++++++++++++-----------= ---- 5 files changed, 76 insertions(+), 37 deletions(-) diff --git a/linux-user/riscv/signal.c b/linux-user/riscv/signal.c index f598d41..ed76f23 100644 --- a/linux-user/riscv/signal.c +++ b/linux-user/riscv/signal.c @@ -83,7 +83,8 @@ static void setup_sigcontext(struct target_sigcontext *sc= , CPURISCVState *env) __put_user(env->fpr[i], &sc->fpr[i]); } =20 - uint32_t fcsr =3D csr_read_helper(env, CSR_FCSR); /*riscv_get_fcsr(env= );*/ + /*riscv_get_fcsr(env);*/ + uint32_t fcsr =3D csr_read_helper(env, CSR_FCSR, false); __put_user(fcsr, &sc->fcsr); } =20 @@ -159,7 +160,7 @@ static void restore_sigcontext(CPURISCVState *env, stru= ct target_sigcontext *sc) =20 uint32_t fcsr; __get_user(fcsr, &sc->fcsr); - csr_write_helper(env, fcsr, CSR_FCSR); + csr_write_helper(env, fcsr, CSR_FCSR, false); } =20 static void restore_ucontext(CPURISCVState *env, struct target_ucontext *u= c) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4ee09b9..29361ca 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -290,8 +290,11 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, } =20 void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, - target_ulong csrno); -target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno); + target_ulong csrno, bool debugger); +target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno, + bool debugger); + +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); =20 #include "exec/cpu-all.h" =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 86f9f47..1abad94 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -526,7 +526,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->p= riv)); s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); - csr_write_helper(env, s, CSR_MSTATUS); + csr_write_helper(env, s, CSR_MSTATUS, false); riscv_set_mode(env, PRV_S); } else { /* No need to check MTVEC for misaligned - lower 2 bits cannot be = set */ @@ -551,7 +551,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->p= riv)); s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); - csr_write_helper(env, s, CSR_MSTATUS); + csr_write_helper(env, s, CSR_MSTATUS, false); riscv_set_mode(env, PRV_M); } /* TODO yield load reservation */ diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 71c3eb1..b06f0fa 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -34,7 +34,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *me= m_buf, int n) } else if (n < 65) { return gdb_get_reg64(mem_buf, env->fpr[n - 33]); } else if (n < 4096 + 65) { - return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65)); + return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65, true)); } return 0; } @@ -57,7 +57,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) env->fpr[n - 33] =3D ldq_p(mem_buf); /* always 64-bit */ return sizeof(uint64_t); } else if (n < 4096 + 65) { - csr_write_helper(env, ldtul_p(mem_buf), n - 65); + csr_write_helper(env, ldtul_p(mem_buf), n - 65, true); } return 0; } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 3726299..3c5641e 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -87,7 +87,7 @@ static void validate_mstatus_fs(CPURISCVState *env, uintp= tr_t ra) * Adapted from Spike's processor_t::set_csr */ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, - target_ulong csrno) + target_ulong csrno, bool debugger) { #ifndef CONFIG_USER_ONLY uint64_t delegable_ints =3D MIP_SSIP | MIP_STIP | MIP_SEIP; @@ -96,15 +96,21 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, =20 switch (csrno) { case CSR_FFLAGS: - validate_mstatus_fs(env, GETPC()); + if (!debugger) { + validate_mstatus_fs(env, GETPC()); + } cpu_riscv_set_fflags(env, val_to_write & (FSR_AEXC >> FSR_AEXC_SHI= FT)); break; case CSR_FRM: - validate_mstatus_fs(env, GETPC()); + if (!debugger) { + validate_mstatus_fs(env, GETPC()); + } env->frm =3D val_to_write & (FSR_RD >> FSR_RD_SHIFT); break; case CSR_FCSR: - validate_mstatus_fs(env, GETPC()); + if (!debugger) { + validate_mstatus_fs(env, GETPC()); + } env->frm =3D (val_to_write & FSR_RD) >> FSR_RD_SHIFT; cpu_riscv_set_fflags(env, (val_to_write & FSR_AEXC) >> FSR_AEXC_SH= IFT); break; @@ -169,7 +175,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, * CLINT, no additional locking is needed for read-modifiy-write * CSR operations */ - qemu_mutex_lock_iothread(); + if (!debugger) { + qemu_mutex_lock_iothread(); + } RISCVCPU *cpu =3D riscv_env_get_cpu(env); riscv_cpu_update_mip(cpu, MIP_SSIP | MIP_STIP, (val_to_write & (MIP_SSIP | MIP_STIP))); @@ -177,7 +185,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, * csrs, csrc on mip.SEIP is not decomposable into separate read a= nd * write steps, so a different implementation is needed */ - qemu_mutex_unlock_iothread(); + if (!debugger) { + qemu_mutex_unlock_iothread(); + } break; } case CSR_MIE: { @@ -247,21 +257,25 @@ void csr_write_helper(CPURISCVState *env, target_ulon= g val_to_write, mask |=3D SSTATUS_MXR; } ms =3D (ms & ~mask) | (val_to_write & mask); - csr_write_helper(env, ms, CSR_MSTATUS); + csr_write_helper(env, ms, CSR_MSTATUS, debugger); break; } case CSR_SIP: { - qemu_mutex_lock_iothread(); + if (!debugger) { + qemu_mutex_lock_iothread(); + } target_ulong next_mip =3D (env->mip & ~env->mideleg) | (val_to_write & env->mideleg); - qemu_mutex_unlock_iothread(); - csr_write_helper(env, next_mip, CSR_MIP); + if (!debugger) { + qemu_mutex_unlock_iothread(); + } + csr_write_helper(env, next_mip, CSR_MIP, debugger); break; } case CSR_SIE: { target_ulong next_mie =3D (env->mie & ~env->mideleg) | (val_to_write & env->mideleg); - csr_write_helper(env, next_mie, CSR_MIE); + csr_write_helper(env, next_mie, CSR_MIE, debugger); break; } case CSR_SATP: /* CSR_SPTBR */ { @@ -371,7 +385,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, do_illegal: #endif default: - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + if (!debugger) { + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } } } =20 @@ -380,7 +396,8 @@ void csr_write_helper(CPURISCVState *env, target_ulong = val_to_write, * * Adapted from Spike's processor_t::get_csr */ -target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) +target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno, + bool debugger) { #ifndef CONFIG_USER_ONLY target_ulong ctr_en =3D env->priv =3D=3D PRV_U ? env->scounteren : @@ -416,13 +433,19 @@ target_ulong csr_read_helper(CPURISCVState *env, targ= et_ulong csrno) =20 switch (csrno) { case CSR_FFLAGS: - validate_mstatus_fs(env, GETPC()); + if (!debugger) { + validate_mstatus_fs(env, GETPC()); + } return cpu_riscv_get_fflags(env); case CSR_FRM: - validate_mstatus_fs(env, GETPC()); + if (!debugger) { + validate_mstatus_fs(env, GETPC()); + } return env->frm; case CSR_FCSR: - validate_mstatus_fs(env, GETPC()); + if (!debugger) { + validate_mstatus_fs(env, GETPC()); + } return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); /* rdtime/rdtimeh is trapped and emulated by bbl in system mode */ @@ -504,9 +527,13 @@ target_ulong csr_read_helper(CPURISCVState *env, targe= t_ulong csrno) return env->mstatus & mask; } case CSR_SIP: { - qemu_mutex_lock_iothread(); + if (!debugger) { + qemu_mutex_lock_iothread(); + } target_ulong tmp =3D env->mip & env->mideleg; - qemu_mutex_unlock_iothread(); + if (!debugger) { + qemu_mutex_unlock_iothread(); + } return tmp; } case CSR_SIE: @@ -539,9 +566,13 @@ target_ulong csr_read_helper(CPURISCVState *env, targe= t_ulong csrno) case CSR_MSTATUS: return env->mstatus; case CSR_MIP: { - qemu_mutex_lock_iothread(); + if (!debugger) { + qemu_mutex_lock_iothread(); + } target_ulong tmp =3D env->mip; - qemu_mutex_unlock_iothread(); + if (!debugger) { + qemu_mutex_unlock_iothread(); + } return tmp; } case CSR_MIE: @@ -601,7 +632,11 @@ target_ulong csr_read_helper(CPURISCVState *env, targe= t_ulong csrno) #endif } /* used by e.g. MTIME read */ - do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + if (!debugger) { + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } else { + return 0; + } } =20 /* @@ -625,8 +660,8 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ul= ong src, target_ulong csr) { validate_csr(env, csr, 1, GETPC()); - uint64_t csr_backup =3D csr_read_helper(env, csr); - csr_write_helper(env, src, csr); + uint64_t csr_backup =3D csr_read_helper(env, csr, false); + csr_write_helper(env, src, csr, false); return csr_backup; } =20 @@ -634,9 +669,9 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ul= ong src, target_ulong csr, target_ulong rs1_pass) { validate_csr(env, csr, rs1_pass !=3D 0, GETPC()); - uint64_t csr_backup =3D csr_read_helper(env, csr); + uint64_t csr_backup =3D csr_read_helper(env, csr, false); if (rs1_pass !=3D 0) { - csr_write_helper(env, src | csr_backup, csr); + csr_write_helper(env, src | csr_backup, csr, false); } return csr_backup; } @@ -645,9 +680,9 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ul= ong src, target_ulong csr, target_ulong rs1_pass) { validate_csr(env, csr, rs1_pass !=3D 0, GETPC()); - uint64_t csr_backup =3D csr_read_helper(env, csr); + uint64_t csr_backup =3D csr_read_helper(env, csr, false); if (rs1_pass !=3D 0) { - csr_write_helper(env, (~src) & csr_backup, csr); + csr_write_helper(env, (~src) & csr_backup, csr, false); } return csr_backup; } @@ -674,7 +709,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) mstatus =3D set_field(mstatus, MSTATUS_SPIE, 0); mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); riscv_set_mode(env, prev_priv); - csr_write_helper(env, mstatus, CSR_MSTATUS); + csr_write_helper(env, mstatus, CSR_MSTATUS, false); =20 return retpc; } @@ -699,7 +734,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulo= ng cpu_pc_deb) mstatus =3D set_field(mstatus, MSTATUS_MPIE, 0); mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); riscv_set_mode(env, prev_priv); - csr_write_helper(env, mstatus, CSR_MSTATUS); + csr_write_helper(env, mstatus, CSR_MSTATUS, false); =20 return retpc; } --=20 2.7.4 From nobody Fri Nov 7 02:16:35 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 5/5 v2] RISC-V: Add hooks to use the gdb xml files. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Jim Wilson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Jim Wilson --- target/riscv/cpu.c | 9 ++++++- target/riscv/gdbstub.c | 73 ++++++++++++++++++++++++++++++++++++++++++++--= ---- 2 files changed, 73 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a025a0a..b248e3e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -305,6 +305,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) return; } =20 + riscv_cpu_register_gdb_regs_for_features(cs); + qemu_init_vcpu(cs); cpu_reset(cs); =20 @@ -345,7 +347,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) cc->synchronize_from_tb =3D riscv_cpu_synchronize_from_tb; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; - cc->gdb_num_core_regs =3D 65; + cc->gdb_num_core_regs =3D 33; +#if defined(TARGET_RISCV32) + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; +#elif defined(TARGET_RISCV64) + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; +#endif cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifdef CONFIG_USER_ONLY diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index b06f0fa..9558d80 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -31,10 +31,6 @@ int riscv_cpu_gdb_read_register(CPUState *cs, uint8_t *m= em_buf, int n) return gdb_get_regl(mem_buf, env->gpr[n]); } else if (n =3D=3D 32) { return gdb_get_regl(mem_buf, env->pc); - } else if (n < 65) { - return gdb_get_reg64(mem_buf, env->fpr[n - 33]); - } else if (n < 4096 + 65) { - return gdb_get_regl(mem_buf, csr_read_helper(env, n - 65, true)); } return 0; } @@ -53,11 +49,72 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) } else if (n =3D=3D 32) { env->pc =3D ldtul_p(mem_buf); return sizeof(target_ulong); - } else if (n < 65) { - env->fpr[n - 33] =3D ldq_p(mem_buf); /* always 64-bit */ + } + return 0; +} + +static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + return gdb_get_reg64(mem_buf, env->fpr[n]); + } else if (n < 35) { + /* + * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we + * subtract 31 to map the gdb FP register number to the CSR number. + * This also works for CSR_FRM and CSR_FCSR. + */ + return gdb_get_regl(mem_buf, csr_read_helper(env, n - 31, true)); + } + return 0; +} + +static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) +{ + if (n < 32) { + env->fpr[n] =3D ldq_p(mem_buf); /* always 64-bit */ return sizeof(uint64_t); - } else if (n < 4096 + 65) { - csr_write_helper(env, ldtul_p(mem_buf), n - 65, true); + } else if (n < 35) { + /* + * CSR_FFLAGS is 0x001, and gdb says it is FP register 32, so we + * subtract 31 to map the gdb FP register number to the CSR number. + * This also works for CSR_FRM and CSR_FCSR. + */ + csr_write_helper(env, ldtul_p(mem_buf), n - 31, true); } return 0; } + +static int riscv_gdb_get_csr(CPURISCVState *env, uint8_t *mem_buf, int n) +{ + if (n < ARRAY_SIZE(csr_register_map)) { + return gdb_get_regl(mem_buf, csr_read_helper(env, csr_register_map= [n], + true)); + } + return 0; +} + +static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) +{ + if (n < ARRAY_SIZE(csr_register_map)) { + csr_write_helper(env, ldtul_p(mem_buf), csr_register_map[n], true); + } + return 0; +} + +void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) +{ + /* ??? Assume all targets have FPU regs for now. */ +#if defined(TARGET_RISCV32) + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + 35, "riscv-32bit-fpu.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, + 4096, "riscv-32bit-csr.xml", 0); +#elif defined(TARGET_RISCV64) + gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, + 35, "riscv-64bit-fpu.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, + 4096, "riscv-64bit-csr.xml", 0); +#endif +} --=20 2.7.4