From nobody Thu May 2 21:15:18 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1542597460066182.94924650960468; Sun, 18 Nov 2018 19:17:40 -0800 (PST) Received: from localhost ([::1]:54107 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gOa3w-00046p-Jr for importer@patchew.org; Sun, 18 Nov 2018 22:17:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37643) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gOa2o-0003id-A4 for qemu-devel@nongnu.org; Sun, 18 Nov 2018 22:16:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gOa2n-0005Qu-9e for qemu-devel@nongnu.org; Sun, 18 Nov 2018 22:16:14 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:40594) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gOa2n-0005Qb-2y for qemu-devel@nongnu.org; Sun, 18 Nov 2018 22:16:13 -0500 Received: by mail-oi1-x243.google.com with SMTP id t204so1331740oie.7 for ; Sun, 18 Nov 2018 19:16:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=aGJAFGSfL/r9NAUCRhPPbQA+ue4K9crikynrNfK7iw4=; b=vTjpcaRCWs4TTcHr4aGDSUBKsVlhvrV13q83g5pFF5u/T+ewvL2ZNeQvb20Mu2I5VU NzIQmcmtT5nj0O+caYD2Bp+aYjAZxRFuSoEPBjsUyYmvd8A/ey3JUhgzLWRrfdUc3HdP MuGGGk8RgEXDBAQJyq9r0I2+wZhy6scsV4s9ftdyy6V+SfmwkChPwLVbTGiAY+KMwYDT yxBFtZAKW9CJ/NN7IwKOJA+zZB2iXjW9O75qJjf0b5xmwZt+TsPpm39kvkEjofFG5BBL 24XGr8hP6gDfmP261wnlMVEerg58AR0teFEZidighcikOJeuP1/TVJNp3KO80LQg1/85 tVnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=aGJAFGSfL/r9NAUCRhPPbQA+ue4K9crikynrNfK7iw4=; b=om8rU6gLXNNtOmoZnnFN9J2PGO8GDrvLTvMxpAgox7b4U4VqC7PvFiJilsmhJNy4Tn PL56Jhv/W7RZRx3UoortvldZptzeHzzUJsJN292cziGFyv+o9klet/VA9UnpnIPKf1c5 S5JwYx/o+rjj7DZLn5YndR7a6WHGnS1bk2Vo5dwUMo7LVve3hyloh7bydxS0RYnu5umC 6yn2FIMe652qfNRCuBtst1Jz3gUUiyDHyLv7zx4iYJ3pZV5ELFAg+w5u7iNUEBZkJdNJ kfjzU+DMG9SD3XdwnmL9Q0o4hvwfGC7dS+53JH/2ZsshcVr8VS24KUWEpH7lF4Hh28W6 YYlA== X-Gm-Message-State: AGRZ1gICe1hGlnN/9aQ3MVdQhjGlLMkICDoTNuvcoKIYHmZ2x1z++G8l ihk4TQIP7sXPPSWkWtJdZy1h+AHgGeVUYXRDeCc= X-Google-Smtp-Source: AJdET5cPskGOVhqVm0vWY8yYhf2DMa88Qe954fZV70bphH7Zkpx7hZZt4DPi8l2dLGi1tegHfvFnHc78FMeqSuMTZZ4= X-Received: by 2002:aca:ab16:: with SMTP id u22mr6404724oie.249.1542597372104; Sun, 18 Nov 2018 19:16:12 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Seth K Date: Sun, 18 Nov 2018 22:15:36 -0500 Message-ID: To: peter.maydell@linaro.org X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 X-Content-Filtered-By: Mailman/MimeDel 2.1.21 Subject: [Qemu-devel] [PATCH] hw/arm/stm32f205: Fix the UART and Timer region size X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Alistair Francis , "qemu-devel@nongnu.org Developers" , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Seth Kintigh I corrected these 2 memory regions based on specifications from the chip manufacturer. The existing ranges seem to overlap and and cause odd behavior and/or crashes when trying to set up multiple UARTs, Signed-off-by: Seth Kintigh Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- Phil, I hope this is the right format. PMM, my original changes were made on an old version, but I made the patch from the latest version per the instructions. I'm glad to hear that serial port limit is gone! hw/char/stm32f2xx_usart.c | 2 +- hw/timer/stm32f2xx_timer.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c index 032b5fda13..f3363a2952 100644 --- a/hw/char/stm32f2xx_usart.c +++ b/hw/char/stm32f2xx_usart.c @@ -202,7 +202,7 @@ static void stm32f2xx_usart_init(Object *obj) sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); memory_region_init_io(&s->mmio, obj, &stm32f2xx_usart_ops, s, - TYPE_STM32F2XX_USART, 0x2000); + TYPE_STM32F2XX_USART, 0x400); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); } diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c index 58fc7b1188..ae744d1642 100644 --- a/hw/timer/stm32f2xx_timer.c +++ b/hw/timer/stm32f2xx_timer.c @@ -308,7 +308,7 @@ static void stm32f2xx_timer_init(Object *obj) sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s, - "stm32f2xx_timer", 0x4000); + "stm32f2xx_timer", 0x400); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrup= t, s); On Thu, Nov 15, 2018 at 7:05 AM Peter Maydell wrote: > On 4 November 2018 at 07:42, Seth K wrote: > > I corrected these 2 memory regions based on specifications from the chip > > manufacturer. The existing ranges seem to overlap and and cause odd > > behavior and/or crashes when trying to set up multiple UARTs, > > I also played with changing MAX_SERIAL_PORTS to 8 to match the hardware, > > but I did not include that in this patch as I never fully tested its > > effects. > > Hi; thanks for the patch. As Philippe says, it looks good, > but the one thing we definitely need is a Signed-off-by: > line from you. > > A minor note -- there is no "MAX_SERIAL_PORTS" definition > in QEMU any more: we removed that artificial limitation > earlier this year. Maybe you're basing your patch on an > older version of QEMU? It's best to use git master for > development. Our SoC model defines 6 uarts (STM_NUM_USARTS) > in hw/arm/stm32f205_soc.c, which should all now be connectable > on the command line, though I haven't tested that or checked > whether the hardware has 6 or some other number... > > thanks > -- PMM >