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Tue, 01 Sep 2026 06:04:28 -0700 (PDT) MIME-Version: 1.0 From: Stanley Jhu Date: Tue, 1 Sep 2026 21:03:52 +0800 X-Gm-Features: AcwNN1WQesaLm-6c_6dsMTJeHwrXmMQl7lGutVxeZ-CH3CyKQ7dKIvnZ8k0UBfc Message-ID: Subject: [PATCH] hw/ufs: Reset controller and MCQ state on HCE transition to 0 To: Jeuk Kim Cc: qemu-devel@nongnu.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=stanleyjhu@google.com; helo=mail-qt1-x82b.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1788267919839154100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to the JEDEC Universal Flash Storage Host Controller Interface (UFSHCI) specification (Section 5.2.1 "Host Controller Enable"): when Host Controller Enable (HCE) transitions from 1 to 0, a host controller reset is initiated. The host controller shall abort all active transfers, return internal state machines to idle, and de-assert all interrupts. Currently, QEMU's UFS emulator only clears HCS and HCE registers upon HCE=3D0, leaving internal state active. Specifically: - Outstanding SCSI requests in the block layer are not purged. - Active bottom halves (doorbell_bh and complete_bh) remain scheduled. - Allocated MCQ Submission and Completion Queues (sq and cq) are not freed. - Dynamic MCQ queue registers and legacy UTRL request states remain stale. Implement ufs_hce_reset() to: 1. Purge outstanding SCSI requests for all logical units via scsi_device_purge_requests(). 2. Cancel active bottom halves (doorbell_bh and complete_bh). 3. Clear standard request list slots and release SGLs via ufs_clear_req(). 4. Free allocated MCQ queues and clear dynamic queue registers while preserving static capability offsets. 5. De-assert interrupts via ufs_irq_check(). 6. Add a trace_ufs_hce_reset() trace event. Signed-off-by: Stanley Jhu --- hw/ufs/trace-events | 1 + hw/ufs/ufs.c | 64 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/hw/ufs/trace-events b/hw/ufs/trace-events index 00e263c7ba..1eb85c6978 100644 --- a/hw/ufs/trace-events +++ b/hw/ufs/trace-events @@ -14,6 +14,7 @@ ufs_process_uiccmd(uint32_t uiccmd, uint32_t ucmdarg1, uint32_t ucmdarg2, uint ufs_mcq_complete_req(uint8_t qid) "sqid %"PRIu8"" ufs_mcq_create_sq(uint8_t sqid, uint8_t cqid, uint64_t addr, uint16_t size) "mcq create sq sqid %"PRIu8", cqid %"PRIu8", addr 0x%"PRIx64", size %"PRIu16"" ufs_mcq_create_cq(uint8_t cqid, uint64_t addr, uint16_t size) "mcq create cq cqid %"PRIu8", addr 0x%"PRIx64", size %"PRIu16"" +ufs_hce_reset(void) "HCE 1 -> 0 reset: cancelling BHs, resetting MCQ and request lists" # error condition ufs_err_dma_read_utrd(uint32_t slot, uint64_t addr) "failed to read utrd. UTRLDBR slot %"PRIu32", UTRD dma addr %"PRIu64"" diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index a8e2df8087..b729b247f1 100644 --- a/hw/ufs/ufs.c +++ b/hw/ufs/ufs.c @@ -679,6 +679,69 @@ static bool ufs_mcq_delete_cq(UfsHc *u, uint8_t qid) return true; } +static void ufs_hce_reset(UfsHc *u) +{ + int i; + + trace_ufs_hce_reset(); + + /* 1. Purge outstanding SCSI requests for all logical units */ + for (i =3D 0; i < UFS_MAX_LUS; i++) { + if (u->lus[i] && u->lus[i]->scsi_dev) { + scsi_device_purge_requests(u->lus[i]->scsi_dev, SENSE_CODE(RES= ET)); + } + } + + /* 2. Cancel active Bottom Halves */ + if (u->doorbell_bh) { + qemu_bh_cancel(u->doorbell_bh); + } + if (u->complete_bh) { + qemu_bh_cancel(u->complete_bh); + } + + /* 3. Reset standard request list slots and doorbells */ + for (i =3D 0; i < u->params.nutrs; i++) { + ufs_clear_req(&u->req_list[i]); + u->req_list[i].state =3D UFS_REQUEST_IDLE; + } + u->reg.utrldbr =3D 0; + u->reg.utmrldbr =3D 0; + u->reg.is =3D 0; + + /* 4. Free MCQ Queues and reset MCQ dynamic registers */ + if (u->params.mcq) { + for (i =3D 0; i < ARRAY_SIZE(u->sq); i++) { + if (u->sq[i]) { + ufs_mcq_free_sq(u->sq[i]); + u->sq[i] =3D NULL; + } + } + for (i =3D 0; i < ARRAY_SIZE(u->cq); i++) { + if (u->cq[i]) { + ufs_mcq_free_cq(u->cq[i]); + u->cq[i] =3D NULL; + } + } + + /* Clear dynamic queue configuration without touching static offse= ts */ + for (i =3D 0; i < ARRAY_SIZE(u->mcq_reg); i++) { + u->mcq_reg[i].sqattr =3D 0; + u->mcq_reg[i].sqlba =3D 0; + u->mcq_reg[i].squba =3D 0; + u->mcq_reg[i].sqcfg =3D 0; + u->mcq_reg[i].cqattr =3D 0; + u->mcq_reg[i].cqlba =3D 0; + u->mcq_reg[i].cquba =3D 0; + u->mcq_reg[i].cqcfg =3D 0; + } + memset(&u->mcq_op_reg, 0, sizeof(u->mcq_op_reg)); + } + + /* 5. De-assert IRQ */ + ufs_irq_check(u); +} + static void ufs_write_reg(UfsHc *u, hwaddr offset, uint32_t data, unsigned size) { switch (offset) { @@ -696,6 +759,7 @@ static void ufs_write_reg(UfsHc *u, hwaddr offset, uint32_t data, unsigned size) u->reg.hce =3D FIELD_DP32(u->reg.hce, HCE, HCE, 1); } else if (FIELD_EX32(u->reg.hce, HCE, HCE) && !FIELD_EX32(data, HCE, HCE)) { + ufs_hce_reset(u); u->reg.hcs =3D 0; u->reg.hce =3D FIELD_DP32(u->reg.hce, HCE, HCE, 0); } -- 2.43.0