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This virtual PCILeec= h device aims to help security researchers attack the guest via DMA and tes= t their IOMMU defenses.
T= his device is intended to support any systems with PCI, but I am only able = to test x86-based guests.
For what PCILeech is, check PCILeech GitHub repository:=C2=A0https://github.com/ufrisk/pcileech=
The QEMU-PCILeech plugin is currently awaiting merging:=C2= =A0https://= github.com/ufrisk/LeechCore-plugins/pull/10

Th= is is my first time contributing to QEMU and I am sorry that I forgot to in= clude a "[PATCH]" prefix in the title from my previous email and = that I didn't cc to relevant maintainers.
If needed, add my n= ame and contact info into the maintainer's list.

Signed-off-by: Zero Tang <z= ero.tangptr@gmail.com>
---
=C2=A0hw/misc/Kconfig =C2=A0 =C2=A0 | =C2=A0= 5 ++++
=C2=A0hw/misc/meson.build | =C2=A0 1 +
=C2=A0hw/misc/pcileech= .c =C2=A0| 291 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++
=C2=A03 files changed, 297 insertions(+)

diff -= -git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 1e08785b83..6c3ea7bf74 10= 0644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -30,6 +30,11 @= @ config EDU
=C2=A0 =C2=A0 =C2=A0default y if TEST_DEVICES
=C2=A0 =C2= =A0 =C2=A0depends on PCI && MSI_NONBROKEN
=C2=A0
+config PCIL= EECH
+ =C2=A0 =C2=A0bool
+ =C2=A0 =C2=A0default y
+ =C2=A0 =C2=A0d= epends on PCI
+
=C2=A0config PCA9552
=C2=A0 =C2=A0 =C2=A0bool
= =C2=A0 =C2=A0 =C2=A0depends on I2C
diff --git a/hw/misc/meson.build b/hw= /misc/meson.build
index 2ca8717be2..e79931b9a6 100644
--- a/hw/misc/m= eson.build
+++ b/hw/misc/meson.build
@@ -1,5 +1,6 @@
=C2=A0system_= ss.add(when: 'CONFIG_APPLESMC', if_true: files('applesmc.c'= ))
=C2=A0system_ss.add(when: 'CONFIG_EDU', if_true: files('e= du.c'))
+system_ss.add(when: 'CONFIG_PCILEECH', if_true: fil= es('pcileech.c'))
=C2=A0system_ss.add(when: 'CONFIG_FW_CFG_D= MA', if_true: files('vmcoreinfo.c'))
=C2=A0system_ss.add(whe= n: 'CONFIG_ISA_DEBUG', if_true: files('debugexit.c'))
= =C2=A0system_ss.add(when: 'CONFIG_ISA_TESTDEV', if_true: files('= ;pc-testdev.c'))
diff --git a/hw/misc/pcileech.c b/hw/misc/pcileech.= c
new file mode 100644
index 0000000000..252a570161
--- /dev/null<= br>+++ b/hw/misc/pcileech.c
@@ -0,0 +1,291 @@
+/*
+ * QEMU Virtual= PCILeech Device
+ *
+ * Copyright (c) 2024 Zero Tang
+ *
+ * P= ermission is hereby granted, free of charge, to any person obtaining a
+= * copy of this software and associated documentation files (the "Soft= ware"),
+ * to deal in the Software without restriction, including = without limitation
+ * the rights to use, copy, modify, merge, publish, = distribute, sublicense,
+ * and/or sell copies of the Software, and to p= ermit persons to whom the
+ * Software is furnished to do so, subject to= the following conditions:
+ *
+ * The above copyright notice and thi= s permission notice shall be included in
+ * all copies or substantial p= ortions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS= ", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING = BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A = PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHOR= S OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIA= BILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *= FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ *= DEALINGS IN THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h&quo= t;
+#include "qemu/units.h"
+#include "hw/pci/pci.h&qu= ot;
+#include "hw/hw.h"
+#include "hw/pci/msi.h"<= br>+#include "qemu/timer.h"
+#include "hw/qdev-properties= .h"
+#include "hw/qdev-properties-system.h"
+#include = "qom/object.h"
+#include "qemu/main-loop.h" /* iothr= ead mutex */
+#include "qemu/module.h"
+#include "qapi= /visitor.h"
+
+#define TYPE_PCILEECH_DEVICE "pcileech"=
+
+struct LeechRequestHeader {
+ =C2=A0 =C2=A0uint8_t endianness;= /* 0 - Little, 1 - Big */
+ =C2=A0 =C2=A0uint8_t command; =C2=A0 =C2=A0= /* 0 - Read, 1 - Write */
+ =C2=A0 =C2=A0uint8_t reserved[6];
+ =C2= =A0 =C2=A0/* Variable Endianness */
+ =C2=A0 =C2=A0uint64_t address;
= + =C2=A0 =C2=A0uint64_t length;
+};
+
+struct LeechResponseHeader = {
+ =C2=A0 =C2=A0uint8_t endianness; /* 0 - Little, 1 - Big */
+ =C2= =A0 =C2=A0uint8_t reserved[3];
+ =C2=A0 =C2=A0MemTxResult result;
+ = =C2=A0 =C2=A0uint64_t length; =C2=A0 =C2=A0/* Indicates length of data foll= owed by header */
+};
+
+/* Verify the header length */
+static= _assert(sizeof(struct LeechRequestHeader) =3D=3D 24);
+static_assert(siz= eof(struct LeechResponseHeader) =3D=3D 16);
+
+struct PciLeechState {=
+ =C2=A0 =C2=A0/* Internal State */
+ =C2=A0 =C2=A0PCIDevice device;=
+ =C2=A0 =C2=A0QemuThread thread;
+ =C2=A0 =C2=A0QemuMutex mutex;+ =C2=A0 =C2=A0bool endianness;
+ =C2=A0 =C2=A0bool stopping;
+ =C2= =A0 =C2=A0/* Communication */
+ =C2=A0 =C2=A0char *host;
+ =C2=A0 =C2= =A0uint16_t port;
+ =C2=A0 =C2=A0int sockfd;
+};
+
+typedef str= uct LeechRequestHeader LeechRequestHeader;
+typedef struct PciLeechState= PciLeechState;
+
+DECLARE_INSTANCE_CHECKER(PciLeechState, PCILEECH, = TYPE_PCILEECH_DEVICE)
+
+static void pci_leech_process_write_request(= PciLeechState *state,
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0LeechRequestHeader *request,
+ =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int in= coming)
+{
+ =C2=A0 =C2=A0char buff[1024];
+ =C2=A0 =C2=A0for (uin= t64_t i =3D 0; i < request->length; i +=3D sizeof(buff)) {
+ =C2= =A0 =C2=A0 =C2=A0 =C2=A0struct LeechResponseHeader response =3D { 0 };
+= =C2=A0 =C2=A0 =C2=A0 =C2=A0char* response_buffer =3D (char *)&response= ;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0const uint64_t writelen =3D (request->= length - i) <=3D sizeof(buff) ?
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (request->length - i) : sizeof(buff);+ =C2=A0 =C2=A0 =C2=A0 =C2=A0ssize_t recvlen =3D 0, sendlen =3D 0;
+ = =C2=A0 =C2=A0 =C2=A0 =C2=A0while (recvlen < writelen) {
+ =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0recvlen +=3D recv(incoming, &buff[recvle= n], writelen - recvlen, 0);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+ =C2=A0 = =C2=A0 =C2=A0 =C2=A0response.endianness =3D state->endianness;
+ =C2= =A0 =C2=A0 =C2=A0 =C2=A0response.result =3D pci_dma_write(&state->de= vice, request->address + i,
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0buff, writelen);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0if= (response.result) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0printf(&= quot;PCILeech: Address 0x%lX Write Error! MemTxResult: 0x%X\n",
+ = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0reques= t->address + i, response.result);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+= =C2=A0 =C2=A0 =C2=A0 =C2=A0response.length =3D 0;
+ =C2=A0 =C2=A0 =C2= =A0 =C2=A0while (sendlen < sizeof(struct LeechResponseHeader)) {
+ = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sendlen +=3D send(incoming, &r= esponse_buffer[sendlen],
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sizeof(struct LeechResp= onseHeader) - sendlen, 0);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+ =C2=A0 = =C2=A0}
+}
+
+static void pci_leech_process_read_request(PciLeechS= tate *state,
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0LeechRequestHeader *request,
+ =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int incoming)=
+{
+ =C2=A0 =C2=A0char buff[1024];
+ =C2=A0 =C2=A0for (uint64_t i= =3D 0; i < request->length; i +=3D sizeof(buff)) {
+ =C2=A0 =C2= =A0 =C2=A0 =C2=A0struct LeechResponseHeader response =3D { 0 };
+ =C2=A0= =C2=A0 =C2=A0 =C2=A0char* response_buffer =3D (char *)&response;
+ = =C2=A0 =C2=A0 =C2=A0 =C2=A0const uint64_t readlen =3D (request->length -= i) <=3D sizeof(buff) ?
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0(request->length - i) : sizeof(buff);
+ =C2=A0 =C2=A0 =C2= =A0 =C2=A0ssize_t sendlen =3D 0;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0response.e= ndianness =3D state->endianness;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0respons= e.result =3D pci_dma_read(&state->device, request->address + i,+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0buff, rea= dlen);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0if (response.result) {
+ =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0printf("PCILeech: Address 0x%lX Read= Error! MemTxResult: 0x%X\n",
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0request->address + i, response.result)= ;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0respons= e.length =3D (request->endianness !=3D state->endianness) ?
+ =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0bswap64(readlen) : readlen;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0while (sendl= en < sizeof(struct LeechResponseHeader)) {
+ =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0sendlen +=3D send(incoming, &response_buffer[sendlen],=
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0sizeof(struct LeechResponseHeader) - sendlen, 0= );
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0sendle= n =3D 0;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0while (sendlen < readlen) {
= + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sendlen +=3D send(incoming, &= ;buff[sendlen], readlen - sendlen, 0);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}+ =C2=A0 =C2=A0}
+}
+
+static void *pci_leech_worker_thread(void = *opaque)
+{
+ =C2=A0 =C2=A0PciLeechState *state =3D PCILEECH(opaque);=
+ =C2=A0 =C2=A0while (1) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0LeechRequest= Header request;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0char *request_buffer =3D (c= har *)&request;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0ssize_t received =3D 0;=
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0int incoming;
+ =C2=A0 =C2=A0 =C2=A0 = =C2=A0struct sockaddr address;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0socklen_t ad= drlen;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Check if we are stopping. */
+= =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_mutex_lock(&state->mutex);
+ =C2= =A0 =C2=A0 =C2=A0 =C2=A0if (state->stopping) {
+ =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0qemu_mutex_unlock(&state->mutex);
+ =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}<= br>+ =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_mutex_unlock(&state->mutex);+ =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Accept PCILeech requests. */
+ =C2=A0 = =C2=A0 =C2=A0 =C2=A0/* Use HTTP1.0-like protocol for simplicity. */
+ = =C2=A0 =C2=A0 =C2=A0 =C2=A0incoming =3D accept(state->sockfd, &addre= ss, &addrlen);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0if (incoming < 0) {+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0puts("WARNING: Failed to = accept socket for PCILeech! Skipping "
+ =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "Request...\n");
+ =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0continue;
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}<= br>+ =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Get PCILeech requests. */
+ =C2=A0 = =C2=A0 =C2=A0 =C2=A0while (received < sizeof(LeechRequestHeader)) {
+= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0received +=3D recv(incoming, &= ;request_buffer[received],
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sizeof(LeechRequestH= eader) - received, 0);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+ =C2=A0 =C2=A0= =C2=A0 =C2=A0/* Swap endianness. */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0if (re= quest.endianness !=3D state->endianness) {
+ =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0request.address =3D bswap64(request.address);
+ =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0request.length =3D bswap64(request.length= );
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Pro= cess PCILeech requests. */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_mutex_lock(= &state->mutex);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0if (request.command)= {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pci_leech_process_write_re= quest(state, &request, incoming);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0} els= e {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pci_leech_process_read_re= quest(state, &request, incoming);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0}
= + =C2=A0 =C2=A0 =C2=A0 =C2=A0qemu_mutex_unlock(&state->mutex);
+ = =C2=A0 =C2=A0 =C2=A0 =C2=A0close(incoming);
+ =C2=A0 =C2=A0}
+ =C2=A0= =C2=A0return NULL;
+}
+
+static void pci_leech_realize(PCIDevice = *pdev, Error **errp)
+{
+ =C2=A0 =C2=A0PciLeechState *state =3D PCILE= ECH(pdev);
+ =C2=A0 =C2=A0struct sockaddr_in sock_addr;
+ =C2=A0 =C2= =A0char host_ip[16];
+ =C2=A0 =C2=A0struct hostent *he =3D gethostbyname= (state->host);
+ =C2=A0 =C2=A0if (he =3D=3D NULL) {
+ =C2=A0 =C2= =A0 =C2=A0 =C2=A0puts("gethostbyname failed!");
+ =C2=A0 =C2= =A0 =C2=A0 =C2=A0exit(EXIT_FAILURE);
+ =C2=A0 =C2=A0}
+ =C2=A0 =C2=A0= /* Initialize the socket for PCILeech. */
+ =C2=A0 =C2=A0state->sockf= d =3D socket(AF_INET, SOCK_STREAM, 0);
+ =C2=A0 =C2=A0if (state->sock= fd < 0) {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0puts("Failed to initializ= e socket for PCILeech!");
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(EXIT_FA= ILURE);
+ =C2=A0 =C2=A0}
+ =C2=A0 =C2=A0sock_addr.sin_family =3D AF_I= NET;
+ =C2=A0 =C2=A0sock_addr.sin_addr =3D *(struct in_addr *)he->h_a= ddr;
+ =C2=A0 =C2=A0sock_addr.sin_port =3D htons(state->port);
+ = =C2=A0 =C2=A0inet_ntop(AF_INET, &sock_addr.sin_addr, host_ip, sizeof(ho= st_ip));
+ =C2=A0 =C2=A0if (bind(state->sockfd, (struct sockaddr *)&a= mp;sock_addr, sizeof(sock_addr))
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0< 0) {
+ =C2= =A0 =C2=A0 =C2=A0 =C2=A0puts("Failed to bind socket for PCILeech!"= ;);
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0close(state->sockfd);
+ =C2=A0 = =C2=A0 =C2=A0 =C2=A0exit(EXIT_FAILURE);
+ =C2=A0 =C2=A0}
+ =C2=A0 =C2= =A0if (listen(state->sockfd, 10) < 0) {
+ =C2=A0 =C2=A0 =C2=A0 =C2= =A0puts("Failed to listen to socket for PCILeech!");
+ =C2=A0 = =C2=A0 =C2=A0 =C2=A0close(state->sockfd);
+ =C2=A0 =C2=A0 =C2=A0 =C2= =A0exit(EXIT_FAILURE);
+ =C2=A0 =C2=A0}
+ =C2=A0 =C2=A0printf("I= NFO: PCILeech is listening on %s:%u...\n", host_ip, state->port);+ =C2=A0 =C2=A0/* Initialize the thread for PCILeech. */
+ =C2=A0 =C2= =A0qemu_mutex_init(&state->mutex);
+ =C2=A0 =C2=A0qemu_thread_cre= ate(&state->thread, "pcileech", pci_leech_worker_thread,+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0state, QEMU_THREAD_JOINABLE);
+}
+
+static void pci_leec= h_finalize(PCIDevice *pdev)
+{
+ =C2=A0 =C2=A0PciLeechState *state = =3D PCILEECH(pdev);
+ =C2=A0 =C2=A0puts("Stopping PCILeech Worker..= .");
+ =C2=A0 =C2=A0qemu_mutex_lock(&state->mutex);
+ =C2= =A0 =C2=A0state->stopping =3D true;
+ =C2=A0 =C2=A0qemu_mutex_unlock(= &state->mutex);
+ =C2=A0 =C2=A0close(state->sockfd);
+ =C2= =A0 =C2=A0qemu_thread_join(&state->thread);
+ =C2=A0 =C2=A0qemu_m= utex_destroy(&state->mutex);
+}
+
+char pci_leech_default_h= ost[] =3D "0.0.0.0";
+
+static void pci_leech_instance_init= (Object *obj)
+{
+ =C2=A0 =C2=A0int x =3D 1;
+ =C2=A0 =C2=A0char* = y =3D (char *)&x;
+ =C2=A0 =C2=A0PciLeechState *state =3D PCILEECH(o= bj);
+ =C2=A0 =C2=A0/* QEMU's String-Property can't specify defa= ult value. */
+ =C2=A0 =C2=A0/* So we have to set the default on our own= . */
+ =C2=A0 =C2=A0if (state->host =3D=3D NULL) {
+ =C2=A0 =C2=A0= =C2=A0 =C2=A0state->host =3D pci_leech_default_host;
+ =C2=A0 =C2=A0= }
+ =C2=A0 =C2=A0/* Save Our Endianness. */
+ =C2=A0 =C2=A0state->= endianness =3D (*y =3D=3D 0);
+}
+
+static Property leech_properti= es[] =3D {
+ =C2=A0 =C2=A0DEFINE_PROP_UINT16("port", PciLeechS= tate, port, 6789),
+ =C2=A0 =C2=A0DEFINE_PROP_STRING("host", P= ciLeechState, host),
+ =C2=A0 =C2=A0DEFINE_PROP_END_OF_LIST(),
+};+
+static void pci_leech_class_init(ObjectClass *class, void *data)
= +{
+ =C2=A0 =C2=A0DeviceClass *dc =3D DEVICE_CLASS(class);
+ =C2=A0 = =C2=A0PCIDeviceClass *k =3D PCI_DEVICE_CLASS(class);
+ =C2=A0 =C2=A0k-&g= t;realize =3D pci_leech_realize;
+ =C2=A0 =C2=A0k->exit =3D pci_leech= _finalize;
+ =C2=A0 =C2=A0/* Change the Vendor/Device ID to your favor. = */
+ =C2=A0 =C2=A0/* These are the default values from PCILeech-FPGA. */=
+ =C2=A0 =C2=A0k->vendor_id =3D PCI_VENDOR_ID_XILINX;
+ =C2=A0 = =C2=A0k->device_id =3D 0x0666;
+ =C2=A0 =C2=A0k->revision =3D 0;+ =C2=A0 =C2=A0k->class_id =3D PCI_CLASS_NETWORK_ETHERNET;
+ =C2=A0= =C2=A0device_class_set_props(dc, leech_properties);
+ =C2=A0 =C2=A0set_= bit(DEVICE_CATEGORY_MISC, dc->categories);
+}
+
+static void pc= i_leech_register_types(void)
+{
+ =C2=A0 =C2=A0static InterfaceInfo i= nterfaces[] =3D {
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0{INTERFACE_CONVENTIONAL_P= CI_DEVICE},
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0{},
+ =C2=A0 =C2=A0};
+ = =C2=A0 =C2=A0static const TypeInfo leech_info =3D {
+ =C2=A0 =C2=A0 =C2= =A0 =C2=A0.name =3D TYPE_PCILEECH_DEVICE,
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0.= parent =3D TYPE_PCI_DEVICE,
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0.instance_size = =3D sizeof(PciLeechState),
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0.instance_init = =3D pci_leech_instance_init,
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0.class_init = =3D pci_leech_class_init,
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0.interfaces =3D i= nterfaces,
+ =C2=A0 =C2=A0};
+ =C2=A0 =C2=A0type_register_static(&= ;leech_info);
+}
+
+type_init(pci_leech_register_types)
= --000000000000c64ce3061f006973--