target/riscv/cpu.c | 12 +++++++----- target/riscv/cpu.h | 1 + 2 files changed, 8 insertions(+), 5 deletions(-)
CPU-specific init functions (riscv_*_cpu_init) configure members of
CPURISCVState, such as priv_version and resetvec. However
riscv_cpu_realize unconditionally overwrites these members. The
result is that some CPUs (such as CPU_SIFIVE_U34) are getting created
with incorrect priv_version.
Only set priv_version in riscv_cpu_realize if priv_spec property was
set. Don't set resetvec in riscv_cpu_realize, rely on the init
function to set it. Set default priv_version and resetvec in init
functions where this was missing.
Signed-off-by: Ivan Grokhotkov <ivan@espressif.com>
---
target/riscv/cpu.c | 12 +++++++-----
target/riscv/cpu.h | 1 +
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f8d07bd20a..8f3cb0c6bf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -110,7 +110,7 @@ static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
- set_priv_version(env, PRIV_VERSION_1_11_0);
+ set_priv_version(env, PRIV_VERSION_DEFAULT);
set_resetvec(env, DEFAULT_RSTVEC);
}
@@ -119,6 +119,8 @@ static void riscv_any_cpu_init(Object *obj)
static void riscv_base32_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_priv_version(env, PRIV_VERSION_DEFAULT);
+ set_resetvec(env, DEFAULT_RSTVEC);
/* We set this in the realise function */
set_misa(env, 0);
}
@@ -157,6 +159,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
static void riscv_base64_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_priv_version(env, PRIV_VERSION_DEFAULT);
+ set_resetvec(env, DEFAULT_RSTVEC);
/* We set this in the realise function */
set_misa(env, 0);
}
@@ -316,7 +320,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
RISCVCPU *cpu = RISCV_CPU(dev);
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
- int priv_version = PRIV_VERSION_1_11_0;
+ int priv_version = PRIV_VERSION_DEFAULT;
target_ulong target_misa = 0;
Error *local_err = NULL;
@@ -339,11 +343,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
cpu->cfg.priv_spec);
return;
}
+ set_priv_version(env, priv_version);
}
- set_priv_version(env, priv_version);
- set_resetvec(env, DEFAULT_RSTVEC);
-
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0adb307f32..88a52a1c8c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,6 +81,7 @@ enum {
#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
+#define PRIV_VERSION_DEFAULT PRIV_VERSION_1_11_0
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
--
2.20.1 (Apple Git-117)
Re-sending with corrected indentation.
---
Best regards,
Ivan Grokhotkov
On Mon, Aug 5, 2019 at 5:14 AM Ivan Grokhotkov <ivan@espressif.com> wrote: > > CPU-specific init functions (riscv_*_cpu_init) configure members of > CPURISCVState, such as priv_version and resetvec. However > riscv_cpu_realize unconditionally overwrites these members. The > result is that some CPUs (such as CPU_SIFIVE_U34) are getting created > with incorrect priv_version. > > Only set priv_version in riscv_cpu_realize if priv_spec property was > set. Don't set resetvec in riscv_cpu_realize, rely on the init > function to set it. Set default priv_version and resetvec in init > functions where this was missing. > > Signed-off-by: Ivan Grokhotkov <ivan@espressif.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 12 +++++++----- > target/riscv/cpu.h | 1 + > 2 files changed, 8 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index f8d07bd20a..8f3cb0c6bf 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -110,7 +110,7 @@ static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); > - set_priv_version(env, PRIV_VERSION_1_11_0); > + set_priv_version(env, PRIV_VERSION_DEFAULT); > set_resetvec(env, DEFAULT_RSTVEC); > } > > @@ -119,6 +119,8 @@ static void riscv_any_cpu_init(Object *obj) > static void riscv_base32_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_priv_version(env, PRIV_VERSION_DEFAULT); > + set_resetvec(env, DEFAULT_RSTVEC); > /* We set this in the realise function */ > set_misa(env, 0); > } > @@ -157,6 +159,8 @@ static void rv32imacu_nommu_cpu_init(Object *obj) > static void riscv_base64_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_priv_version(env, PRIV_VERSION_DEFAULT); > + set_resetvec(env, DEFAULT_RSTVEC); > /* We set this in the realise function */ > set_misa(env, 0); > } > @@ -316,7 +320,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > RISCVCPU *cpu = RISCV_CPU(dev); > CPURISCVState *env = &cpu->env; > RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); > - int priv_version = PRIV_VERSION_1_11_0; > + int priv_version = PRIV_VERSION_DEFAULT; > target_ulong target_misa = 0; > Error *local_err = NULL; > > @@ -339,11 +343,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > cpu->cfg.priv_spec); > return; > } > + set_priv_version(env, priv_version); > } > > - set_priv_version(env, priv_version); > - set_resetvec(env, DEFAULT_RSTVEC); > - > if (cpu->cfg.mmu) { > set_feature(env, RISCV_FEATURE_MMU); > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 0adb307f32..88a52a1c8c 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -81,6 +81,7 @@ enum { > #define PRIV_VERSION_1_09_1 0x00010901 > #define PRIV_VERSION_1_10_0 0x00011000 > #define PRIV_VERSION_1_11_0 0x00011100 > +#define PRIV_VERSION_DEFAULT PRIV_VERSION_1_11_0 > > #define TRANSLATE_PMP_FAIL 2 > #define TRANSLATE_FAIL 1 > -- > 2.20.1 (Apple Git-117) > > > > Re-sending with corrected indentation. Just for future reference this should go below: Signed-off-by: Ivan Grokhotkov <ivan@espressif.com> --- ^ This line. Alistair > > --- > Best regards, > Ivan Grokhotkov > > >
© 2016 - 2024 Red Hat, Inc.