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Sat, 07 Mar 2026 23:20:49 -0800 (PST) From: Chao Liu To: Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Fabiano Rosas , Laurent Vivier Cc: tangtao1634@phytium.com.cn, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 23/28] hw/riscv/virt: integrate the Debug Module Date: Sun, 8 Mar 2026 15:17:26 +0800 Message-ID: <9d4f695c95229e5b28247c477f2278294f5b2cbb.1772936778.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1341; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-dy1-x1341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1772954544767154100 Content-Type: text/plain; charset="utf-8" Expand the VIRT_DEBUG memory map entry from 0x100 to RISCV_DM_SIZE (0x1000 =3D 4 KiB) to accommodate the full Debug Module address space: DMI registers, work area, and ROM entry vector. Create the Debug Module device via riscv_dm_create() and wire each hart's halt-request GPIO to it. Set dm_halt_addr so the CPU enters the DM ROM entry point on debug-mode entry. Signed-off-by: Chao Liu --- hw/riscv/virt.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index bbce2fb667..0a7e29a743 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -58,6 +58,7 @@ #include "qapi/qapi-visit-common.h" #include "hw/virtio/virtio-iommu.h" #include "hw/uefi/var-service-api.h" +#include "hw/riscv/dm.h" =20 /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU= . */ static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type) @@ -80,7 +81,7 @@ static bool virt_aclint_allowed(void) } =20 static const MemMapEntry virt_memmap[] =3D { - [VIRT_DEBUG] =3D { 0x0, 0x100 }, + [VIRT_DEBUG] =3D { 0x0, RISCV_DM_SIZE }, [VIRT_MROM] =3D { 0x1000, 0xf000 }, [VIRT_TEST] =3D { 0x100000, 0x1000 }, [VIRT_RTC] =3D { 0x101000, 0x1000 }, @@ -1702,6 +1703,24 @@ static void virt_machine_init(MachineState *machine) =20 create_platform_bus(s, mmio_irqchip); =20 + /* Create Debug Module and connect each hart's halt-request IRQ */ + int total_harts =3D machine->smp.cpus; + DeviceState *dm =3D riscv_dm_create(system_memory, + s->memmap[VIRT_DEBUG].base, + total_harts); + + for (int h =3D 0; h < total_harts; h++) { + CPUState *cs =3D qemu_get_cpu(h); + RISCVCPU *rcpu =3D RISCV_CPU(cs); + + qdev_connect_gpio_out(dm, h, + qdev_get_gpio_in_named(DEVICE(cs), + "dm-halt-req", 0)); + rcpu->env.dm_rom_present =3D true; + rcpu->env.dm_halt_addr =3D s->memmap[VIRT_DEBUG].base + + RISCV_DM_ROM_ENTRY; + } + serial_mm_init(system_memory, s->memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(mmio_irqchip, UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); --=20 2.53.0