From nobody Wed Nov 19 13:58:01 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu ARC-Seal: i=1; a=rsa-sha256; t=1615945109; cv=none; d=zohomail.com; s=zohoarc; b=P/9y6i4mFjxDlFVwU8D3dJb+I66qQMRI3+hiJlbNw3x5VGXH+uxBlYBhZD1XS4R6nmdqaQ+iFln9FXEpjzvqpt2LR9Gnh5M+lXuChUEVGMB2m3kbToKT7EIfaDcRzwiA0PiWFbBTjE0noAsUCGmHcC02P4/LSfw91SvhFmhLbrs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1615945109; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cwAQXwtxXLYG4olpTeN9jA//s5b5YHREfPm6tS/eT4Y=; b=LTiUPuDTnDbh6P171L1Jh3zS+LQyVIwWaOwKdiXV9WAGlcoui16XqmkBYOjO9tQHkcy//pd8BefeXfYBnundKAMF3+umc7v950XL74KTnIy4dqZnUMJcdZTKhHV5m8Gw4zHXRVTHk8PPTWkcyoRBeN733cKRksPqW9Q8hyY71Xg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1615945109008474.0742915465971; Tue, 16 Mar 2021 18:38:29 -0700 (PDT) Received: from localhost ([::1]:53398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lML8l-0000KK-Nk for importer@patchew.org; Tue, 16 Mar 2021 21:38:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50278) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMKyj-0008SE-U8; Tue, 16 Mar 2021 21:28:07 -0400 Received: from zero.eik.bme.hu ([2001:738:2001:2001::2001]:59596) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMKyY-0000T7-G1; Tue, 16 Mar 2021 21:28:05 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 0B95A746420; Wed, 17 Mar 2021 02:27:52 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 7E7357463A6; Wed, 17 Mar 2021 02:27:51 +0100 (CET) Message-Id: <9c673dfc451cb6a7fd5a55bed00b201a445c7480.1615943871.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v10 1/7] vt82c686: QOM-ify superio related functionality Date: Wed, 17 Mar 2021 02:17:51 +0100 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:738:2001:2001::2001; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Paolo Bonzini , f4bug@amsat.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Collect superio functionality and its controlling config registers handling in an abstract VIA_SUPERIO class that is a subclass of ISA_SUPERIO and put vt82c686b specific parts in a subclass of this abstract class. Signed-off-by: BALATON Zoltan Reviewed-by: Mark Cave-Ayland --- hw/isa/vt82c686.c | 196 +++++++++++++++++++++++++------------- include/hw/isa/vt82c686.h | 1 - 2 files changed, 132 insertions(+), 65 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 05d084f698..6fb81c4ac6 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -249,15 +249,80 @@ static const TypeInfo vt8231_pm_info =3D { }; =20 =20 -typedef struct SuperIOConfig { +#define TYPE_VIA_SUPERIO "via-superio" +OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO) + +struct ViaSuperIOState { + ISASuperIODevice superio; uint8_t regs[0x100]; + const MemoryRegionOps *io_ops; MemoryRegion io; -} SuperIOConfig; +}; + +static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable) +{ + memory_region_set_enabled(&s->io, enable); +} + +static void via_superio_realize(DeviceState *d, Error **errp) +{ + ViaSuperIOState *s =3D VIA_SUPERIO(d); + ISASuperIOClass *ic =3D ISA_SUPERIO_GET_CLASS(s); + Error *local_err =3D NULL; + + assert(s->io_ops); + ic->parent_realize(d, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", = 2); + memory_region_set_enabled(&s->io, false); + /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway = */ + memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0, + &s->io); +} + +static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned s= ize) +{ + ViaSuperIOState *sc =3D opaque; + uint8_t idx =3D sc->regs[0]; + uint8_t val =3D sc->regs[idx]; + + if (addr =3D=3D 0) { + return idx; + } + if (addr =3D=3D 1 && idx =3D=3D 0) { + val =3D 0; /* reading reg 0 where we store index value */ + } + trace_via_superio_read(idx, val); + return val; +} + +static void via_superio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ISASuperIOClass *sc =3D ISA_SUPERIO_CLASS(klass); + + sc->parent_realize =3D dc->realize; + dc->realize =3D via_superio_realize; +} + +static const TypeInfo via_superio_info =3D { + .name =3D TYPE_VIA_SUPERIO, + .parent =3D TYPE_ISA_SUPERIO, + .instance_size =3D sizeof(ViaSuperIOState), + .class_size =3D sizeof(ISASuperIOClass), + .class_init =3D via_superio_class_init, + .abstract =3D true, +}; + +#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" =20 -static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, - unsigned size) +static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) { - SuperIOConfig *sc =3D opaque; + ViaSuperIOState *sc =3D opaque; uint8_t idx =3D sc->regs[0]; =20 if (addr =3D=3D 0) { /* config index register */ @@ -288,25 +353,9 @@ static void superio_cfg_write(void *opaque, hwaddr add= r, uint64_t data, sc->regs[idx] =3D data; } =20 -static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) -{ - SuperIOConfig *sc =3D opaque; - uint8_t idx =3D sc->regs[0]; - uint8_t val =3D sc->regs[idx]; - - if (addr =3D=3D 0) { - return idx; - } - if (addr =3D=3D 1 && idx =3D=3D 0) { - val =3D 0; /* reading reg 0 where we store index value */ - } - trace_via_superio_read(idx, val); - return val; -} - -static const MemoryRegionOps superio_cfg_ops =3D { - .read =3D superio_cfg_read, - .write =3D superio_cfg_write, +static const MemoryRegionOps vt82c686b_superio_cfg_ops =3D { + .read =3D via_superio_cfg_read, + .write =3D vt82c686b_superio_cfg_write, .endianness =3D DEVICE_NATIVE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -314,13 +363,66 @@ static const MemoryRegionOps superio_cfg_ops =3D { }, }; =20 +static void vt82c686b_superio_reset(DeviceState *dev) +{ + ViaSuperIOState *s =3D VIA_SUPERIO(dev); + + memset(s->regs, 0, sizeof(s->regs)); + /* Device ID */ + vt82c686b_superio_cfg_write(s, 0, 0xe0, 1); + vt82c686b_superio_cfg_write(s, 1, 0x3c, 1); + /* Function select - all disabled */ + vt82c686b_superio_cfg_write(s, 0, 0xe2, 1); + vt82c686b_superio_cfg_write(s, 1, 0x03, 1); + /* Floppy ctrl base addr 0x3f0-7 */ + vt82c686b_superio_cfg_write(s, 0, 0xe3, 1); + vt82c686b_superio_cfg_write(s, 1, 0xfc, 1); + /* Parallel port base addr 0x378-f */ + vt82c686b_superio_cfg_write(s, 0, 0xe6, 1); + vt82c686b_superio_cfg_write(s, 1, 0xde, 1); + /* Serial port 1 base addr 0x3f8-f */ + vt82c686b_superio_cfg_write(s, 0, 0xe7, 1); + vt82c686b_superio_cfg_write(s, 1, 0xfe, 1); + /* Serial port 2 base addr 0x2f8-f */ + vt82c686b_superio_cfg_write(s, 0, 0xe8, 1); + vt82c686b_superio_cfg_write(s, 1, 0xbe, 1); + + vt82c686b_superio_cfg_write(s, 0, 0, 1); +} + +static void vt82c686b_superio_init(Object *obj) +{ + VIA_SUPERIO(obj)->io_ops =3D &vt82c686b_superio_cfg_ops; +} + +static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ISASuperIOClass *sc =3D ISA_SUPERIO_CLASS(klass); + + dc->reset =3D vt82c686b_superio_reset; + sc->serial.count =3D 2; + sc->parallel.count =3D 1; + sc->ide.count =3D 0; /* emulated by via-ide */ + sc->floppy.count =3D 1; +} + +static const TypeInfo vt82c686b_superio_info =3D { + .name =3D TYPE_VT82C686B_SUPERIO, + .parent =3D TYPE_VIA_SUPERIO, + .instance_size =3D sizeof(ViaSuperIOState), + .instance_init =3D vt82c686b_superio_init, + .class_size =3D sizeof(ISASuperIOClass), + .class_init =3D vt82c686b_superio_class_init, +}; + =20 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) =20 struct VT82C686BISAState { PCIDevice dev; qemu_irq cpu_intr; - SuperIOConfig superio_cfg; + ViaSuperIOState *via_sio; }; =20 static void via_isa_request_i8259_irq(void *opaque, int irq, int level) @@ -338,7 +440,7 @@ static void vt82c686b_write_config(PCIDevice *d, uint32= _t addr, pci_default_write_config(d, addr, val, len); if (addr =3D=3D 0x85) { /* BIT(1): enable or disable superio config io ports */ - memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1)); + via_superio_io_enable(s->via_sio, val & BIT(1)); } } =20 @@ -370,13 +472,6 @@ static void vt82c686b_isa_reset(DeviceState *dev) pci_conf[0x5a] =3D 0x04; /* KBC/RTC Control*/ pci_conf[0x5f] =3D 0x04; pci_conf[0x77] =3D 0x10; /* GPIO Control 1/2/3/4 */ - - s->superio_cfg.regs[0xe0] =3D 0x3c; /* Device ID */ - s->superio_cfg.regs[0xe2] =3D 0x03; /* Function select */ - s->superio_cfg.regs[0xe3] =3D 0xfc; /* Floppy ctrl base addr */ - s->superio_cfg.regs[0xe6] =3D 0xde; /* Parallel port base addr */ - s->superio_cfg.regs[0xe7] =3D 0xfe; /* Serial port 1 base addr */ - s->superio_cfg.regs[0xe8] =3D 0xbe; /* Serial port 2 base addr */ } =20 static void vt82c686b_realize(PCIDevice *d, Error **errp) @@ -394,7 +489,8 @@ static void vt82c686b_realize(PCIDevice *d, Error **err= p) isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); i8254_pit_init(isa_bus, 0x40, 0, NULL); i8257_dma_init(isa_bus, 0); - isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO); + s->via_sio =3D VIA_SUPERIO(isa_create_simple(isa_bus, + TYPE_VT82C686B_SUPERIO)); mc146818_rtc_init(isa_bus, 2000, NULL); =20 for (i =3D 0; i < PCI_CONFIG_HEADER_SIZE; i++) { @@ -402,16 +498,6 @@ static void vt82c686b_realize(PCIDevice *d, Error **er= rp) d->wmask[i] =3D 0; } } - - memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops, - &s->superio_cfg, "superio_cfg", 2); - memory_region_set_enabled(&s->superio_cfg.io, false); - /* - * The floppy also uses 0x3f0 and 0x3f1. - * But we do not emulate a floppy, so just set it here. - */ - memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, - &s->superio_cfg.io); } =20 static void via_class_init(ObjectClass *klass, void *data) @@ -447,32 +533,14 @@ static const TypeInfo via_info =3D { }; =20 =20 -static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) -{ - ISASuperIOClass *sc =3D ISA_SUPERIO_CLASS(klass); - - sc->serial.count =3D 2; - sc->parallel.count =3D 1; - sc->ide.count =3D 0; - sc->floppy.count =3D 1; -} - -static const TypeInfo via_superio_info =3D { - .name =3D TYPE_VT82C686B_SUPERIO, - .parent =3D TYPE_ISA_SUPERIO, - .instance_size =3D sizeof(ISASuperIODevice), - .class_size =3D sizeof(ISASuperIOClass), - .class_init =3D vt82c686b_superio_class_init, -}; - - static void vt82c686b_register_types(void) { type_register_static(&via_pm_info); type_register_static(&vt82c686b_pm_info); type_register_static(&vt8231_pm_info); - type_register_static(&via_info); type_register_static(&via_superio_info); + type_register_static(&vt82c686b_superio_info); + type_register_static(&via_info); } =20 type_init(vt82c686b_register_types) diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h index 9b6d610e83..0692b9a527 100644 --- a/include/hw/isa/vt82c686.h +++ b/include/hw/isa/vt82c686.h @@ -2,7 +2,6 @@ #define HW_VT82C686_H =20 #define TYPE_VT82C686B_ISA "vt82c686b-isa" -#define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" #define TYPE_VT82C686B_PM "vt82c686b-pm" #define TYPE_VT8231_PM "vt8231-pm" #define TYPE_VIA_AC97 "via-ac97" --=20 2.21.4