From nobody Mon Feb 9 21:01:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=irq.a4lg.com ARC-Seal: i=1; a=rsa-sha256; t=1654257188; cv=none; d=zohomail.com; s=zohoarc; b=ExjmggGipnQ5IOZzS/hKQdBrIbZARPXLZ8Sp6xx3XZP1XHNAr1EmeTdX0GnI5orBducdK+Pi+rQ3+8iNiQDWjJoBCN4bJ2C0sbAohuZkysPi7G6oxgrI8SGsWDs35gKZi1Fj1RoyFNPUm8ymihTJoBVa1eJUeu+gBM3Is1N9rJM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654257188; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8Nn5Zhw/1XD5Dvkf9GOpgoxDYIXc9JhR0kUP1ltqkBE=; b=DeBM75kTkC8BEOE9O66JBxc+JzI22149X92nHAhvvRkLm5hiKqWvRCt/LbJzkwlfr28QmDftC1+KJ54qt9cFyVYnwFs6yr0HUM1udZEwXWSpPw8YpOx9feIyr1Ybl39u4wvoDmr9b1EoFFn3Ijs+R+qYVSrvlYI2RG1iDad2qWs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654257188339186.9576746656012; Fri, 3 Jun 2022 04:53:08 -0700 (PDT) Received: from localhost ([::1]:37118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nx5rX-0001wJ-0Z for importer@patchew.org; Fri, 03 Jun 2022 07:53:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nx5c6-0002uP-8u; Fri, 03 Jun 2022 07:37:15 -0400 Received: from mail-sender.a4lg.com ([153.120.152.154]:64936 helo=mail-sender-0.a4lg.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nx5bw-0002Wj-Tm; Fri, 03 Jun 2022 07:37:02 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id B644D30008B; Fri, 3 Jun 2022 11:36:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irq.a4lg.com; s=2017s01; t=1654256218; bh=8Nn5Zhw/1XD5Dvkf9GOpgoxDYIXc9JhR0kUP1ltqkBE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Mime-Version:Content-Transfer-Encoding; b=KastIkm8U1E3OByu4Hd2UXJyUDcIvLAJmq1whTDq4YaT3ItZAYfwj9v7lQnDvdqjQ xY8GrnhQzO+zi6FGg9xhd/n8oE1+ci3nvcH+Y6QzAuYg1ZdqrdaDFmUjcrgzw5PP73 JZpCLXIEUW9a6PJkL/n4rOdSWN/nouTE+YhOv0Vs= From: Tsukasa OI To: Tsukasa OI , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 2/3] target/riscv: Make CPU property names lowercase Date: Fri, 3 Jun 2022 20:36:43 +0900 Message-Id: <9c2b3ae5456566a098907e1e33c39c98b523ecea.1654256190.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=153.120.152.154; envelope-from=research_trasio@irq.a4lg.com; helo=mail-sender-0.a4lg.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @irq.a4lg.com) X-ZM-MESSAGEID: 1654257189121100001 Content-Type: text/plain; charset="utf-8" Many CPU properties for RISC-V are in lowercase except those with "capitalized" (or CamelCase) names: - Counters - Zifencei - Zicsr - Zfh - Zfhmin - Zve32f - Zve64f This commit makes lowercase names primary but keeps capitalized names as aliases (for backward compatibility, but with deprecated status). Signed-off-by: Tsukasa OI Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3f21563f2d..83262586e4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -840,6 +840,10 @@ static void riscv_cpu_init(Object *obj) } =20 static Property riscv_cpu_properties[] =3D { + /* + * Names for ISA extensions and features should be in lowercase. + */ + /* Base ISA and single-letter standard extensions */ DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), @@ -855,11 +859,11 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), =20 /* Standard unprivileged extensions */ - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), + DEFINE_PROP_BOOL("zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("zifencei", RISCVCPU, cfg.ext_ifencei, true), =20 - DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), - DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), + DEFINE_PROP_BOOL("zfh", RISCVCPU, cfg.ext_zfh, false), + DEFINE_PROP_BOOL("zfhmin", RISCVCPU, cfg.ext_zfhmin, false), DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), @@ -884,8 +888,8 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), =20 - DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), - DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), + DEFINE_PROP_BOOL("zve32f", RISCVCPU, cfg.ext_zve32f, false), + DEFINE_PROP_BOOL("zve64f", RISCVCPU, cfg.ext_zve64f, false), =20 /* Standard supervisor-level extensions */ DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), @@ -893,7 +897,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), =20 /* Base features */ - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), @@ -922,6 +926,15 @@ static Property riscv_cpu_properties[] =3D { /* Other options */ DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, f= alse), =20 + /* Capitalized aliases (deprecated and will be removed) */ + DEFINE_PROP("Counters", RISCVCPU, cfg.ext_counters, qdev_prop_bool, bo= ol), + DEFINE_PROP("Zifencei", RISCVCPU, cfg.ext_ifencei, qdev_prop_bool, boo= l), + DEFINE_PROP("Zicsr", RISCVCPU, cfg.ext_icsr, qdev_prop_bool, bool), + DEFINE_PROP("Zfh", RISCVCPU, cfg.ext_zfh, qdev_prop_bool, bool), + DEFINE_PROP("Zfhmin", RISCVCPU, cfg.ext_zfhmin, qdev_prop_bool, bool), + DEFINE_PROP("Zve32f", RISCVCPU, cfg.ext_zve32f, qdev_prop_bool, bool), + DEFINE_PROP("Zve64f", RISCVCPU, cfg.ext_zve64f, qdev_prop_bool, bool), + DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.34.1