From nobody Sun Feb 8 18:32:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=eik.bme.hu Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1663157436604859.643600915057; Wed, 14 Sep 2022 05:10:36 -0700 (PDT) Received: from localhost ([::1]:50314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oYRDu-000072-Ev for importer@patchew.org; Wed, 14 Sep 2022 08:10:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYQfR-0005FD-8H; Wed, 14 Sep 2022 07:34:58 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:42910) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oYQfP-0005eZ-0a; Wed, 14 Sep 2022 07:34:56 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 74655746397; Wed, 14 Sep 2022 13:34:33 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 24F0C74632B; Wed, 14 Sep 2022 13:34:33 +0200 (CEST) Message-Id: <9b75f6d3d2fc3f8e838a1a9b632b41e0faec2d89.1663154398.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v4 19/21] ppc4xx_sdram: Generalise bank setup MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: clg@kaod.org, Daniel Henrique Barboza , Peter Maydell Date: Wed, 14 Sep 2022 13:34:33 +0200 (CEST) X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1663157437656100001 Content-Type: text/plain; charset="utf-8" Currently only base and size are set on initial bank creation and bcr value is computed on mapping the region. Set bcr at init so the bcr encoding method becomes local to the controller model and mapping and unmapping can operate on the bank so it can be shared between different controller models. This patch converts the DDR2 controller. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_sdram.c | 93 ++++++++++++++++++++++--------------------- hw/ppc/trace-events | 1 + 2 files changed, 48 insertions(+), 46 deletions(-) diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index 611dc7594b..c0cc7f6735 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -106,6 +106,7 @@ static void ppc4xx_sdram_banks(MemoryRegion *ram, int n= r_banks, =20 static void sdram_bank_map(Ppc4xxSdramBank *bank) { + trace_ppc4xx_sdram_map(bank->base, bank->size); memory_region_init(&bank->container, NULL, "sdram-container", bank->si= ze); memory_region_add_subregion(&bank->container, 0, &bank->ram); memory_region_add_subregion(get_system_memory(), bank->base, @@ -114,11 +115,26 @@ static void sdram_bank_map(Ppc4xxSdramBank *bank) =20 static void sdram_bank_unmap(Ppc4xxSdramBank *bank) { + trace_ppc4xx_sdram_unmap(bank->base, bank->size); memory_region_del_subregion(get_system_memory(), &bank->container); memory_region_del_subregion(&bank->container, &bank->ram); object_unparent(OBJECT(&bank->container)); } =20 +static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr, + hwaddr base, hwaddr size, int enabled) +{ + if (memory_region_is_mapped(&bank->container)) { + sdram_bank_unmap(bank); + } + bank->bcr =3D bcr; + bank->base =3D base; + bank->size =3D size; + if (enabled && (bcr & 1)) { + sdram_bank_map(bank); + } +} + /*************************************************************************= ****/ /* DDR SDRAM controller */ static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size) @@ -445,6 +461,8 @@ static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc= , void *data) =20 /*************************************************************************= ****/ /* DDR2 SDRAM controller */ +#define SDRAM_DDR2_BCR_MASK 0xffe0ffc1 + enum { SDRAM_R0BAS =3D 0x40, SDRAM_R1BAS, @@ -518,50 +536,6 @@ static hwaddr sdram_ddr2_size(uint32_t bcr) return size; } =20 -static void sdram_ddr2_set_bcr(Ppc4xxSdramDdr2State *sdram, int i, - uint32_t bcr, int enabled) -{ - if (sdram->bank[i].bcr & 1) { - /* First unmap RAM if enabled */ - trace_ppc4xx_sdram_unmap(sdram_ddr2_base(sdram->bank[i].bcr), - sdram_ddr2_size(sdram->bank[i].bcr)); - sdram_bank_unmap(&sdram->bank[i]); - } - sdram->bank[i].bcr =3D bcr & 0xffe0ffc1; - sdram->bank[i].base =3D sdram_ddr2_base(bcr); - sdram->bank[i].size =3D sdram_ddr2_size(bcr); - if (enabled && (bcr & 1)) { - trace_ppc4xx_sdram_map(sdram_ddr2_base(bcr), sdram_ddr2_size(bcr)); - sdram_bank_map(&sdram->bank[i]); - } -} - -static void sdram_ddr2_map_bcr(Ppc4xxSdramDdr2State *sdram) -{ - int i; - - for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size) { - sdram_ddr2_set_bcr(sdram, i, - sdram_ddr2_bcr(sdram->bank[i].base, - sdram->bank[i].size), 1); - } else { - sdram_ddr2_set_bcr(sdram, i, 0, 0); - } - } -} - -static void sdram_ddr2_unmap_bcr(Ppc4xxSdramDdr2State *sdram) -{ - int i; - - for (i =3D 0; i < sdram->nbanks; i++) { - if (sdram->bank[i].size) { - sdram_ddr2_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0); - } - } -} - static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn) { Ppc4xxSdramDdr2State *s =3D opaque; @@ -620,6 +594,7 @@ static uint32_t sdram_ddr2_dcr_read(void *opaque, int d= crn) static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val) { Ppc4xxSdramDdr2State *s =3D opaque; + int i; =20 switch (dcrn) { case SDRAM_R0BAS: @@ -644,13 +619,25 @@ static void sdram_ddr2_dcr_write(void *opaque, int dc= rn, uint32_t val) (val & SDRAM_DDR2_MCOPT2_DCEN)) { trace_ppc4xx_sdram_enable("enable"); /* validate all RAM mappings */ - sdram_ddr2_map_bcr(s); + for (i =3D 0; i < s->nbanks; i++) { + if (s->bank[i].size) { + sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, + s->bank[i].base, s->bank[i].siz= e, + 1); + } + } s->mcopt2 |=3D SDRAM_DDR2_MCOPT2_DCEN; } else if ((s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) && !(val & SDRAM_DDR2_MCOPT2_DCEN)) { trace_ppc4xx_sdram_enable("disable"); /* invalidate all RAM mappings */ - sdram_ddr2_unmap_bcr(s); + for (i =3D 0; i < s->nbanks; i++) { + if (s->bank[i].size) { + sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, + s->bank[i].base, s->bank[i].siz= e, + 0); + } + } s->mcopt2 &=3D ~SDRAM_DDR2_MCOPT2_DCEN; } break; @@ -679,6 +666,7 @@ static void ppc4xx_sdram_ddr2_realize(DeviceState *dev,= Error **errp) 4 * GiB, 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * M= iB, 32 * MiB, 16 * MiB, 8 * MiB, 0 }; + int i; =20 if (s->nbanks < 1 || s->nbanks > 4) { error_setg(errp, "Invalid number of RAM banks"); @@ -689,6 +677,19 @@ static void ppc4xx_sdram_ddr2_realize(DeviceState *dev= , Error **errp) return; } ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank, valid_bank_sizes); + for (i =3D 0; i < s->nbanks; i++) { + if (s->bank[i].size) { + s->bank[i].bcr =3D sdram_ddr2_bcr(s->bank[i].base, s->bank[i].= size); + s->bank[i].bcr &=3D SDRAM_DDR2_BCR_MASK; + sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr, + s->bank[i].base, s->bank[i].size, 0); + } else { + sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0); + } + trace_ppc4xx_sdram_init(sdram_ddr2_base(s->bank[i].bcr), + sdram_ddr2_size(s->bank[i].bcr), + s->bank[i].bcr); + } =20 ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR, s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write); diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index a07d5aca0f..3b3e4211d4 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -179,3 +179,4 @@ ppc405ep_clocks_setup(const char *trace) "%s" ppc4xx_sdram_enable(const char *trace) "%s SDRAM controller" ppc4xx_sdram_unmap(uint64_t addr, uint64_t size) "Unmap RAM area 0x%" PRIx= 64 " size 0x%" PRIx64 ppc4xx_sdram_map(uint64_t addr, uint64_t size) "Map RAM area 0x%" PRIx64 "= size 0x%" PRIx64 +ppc4xx_sdram_init(uint64_t base, uint64_t size, uint32_t bcr) "Init RAM ar= ea 0x%" PRIx64 " size 0x%" PRIx64 " bcr 0x%x" --=20 2.30.4