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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=40290bcd2=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/20 12:36:38 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, philmd@redhat.com, palmer@dabbelt.com, bmeng.cn@gmail.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Alistair Francis --- include/hw/riscv/sifive_e.h | 1 + hw/riscv/sifive_e.c | 35 +++++++++++++++++++++++++++++++---- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 414992119e..0d3cd07fcc 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -45,6 +45,7 @@ typedef struct SiFiveEState { =20 /*< public >*/ SiFiveESoCState soc; + bool revb; } SiFiveEState; =20 #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e") diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 472a98970b..cb7818341b 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -98,10 +98,14 @@ static void riscv_sifive_e_init(MachineState *machine) memmap[SIFIVE_E_DTIM].base, main_mem); =20 /* Mask ROM reset vector */ - uint32_t reset_vec[2] =3D { - 0x204002b7, /* 0x1000: lui t0,0x20400 */ - 0x00028067, /* 0x1004: jr t0 */ - }; + uint32_t reset_vec[2]; + + if (s->revb) { + reset_vec[0] =3D 0x200102b7; /* 0x1000: lui t0,0x20010 = */ + } else { + reset_vec[0] =3D 0x204002b7; /* 0x1000: lui t0,0x20400 = */ + } + reset_vec[1] =3D 0x00028067; /* 0x1004: jr t0 */ =20 /* copy in the reset vector in little_endian byte order */ for (i =3D 0; i < sizeof(reset_vec) >> 2; i++) { @@ -115,8 +119,31 @@ static void riscv_sifive_e_init(MachineState *machine) } } =20 +static bool sifive_e_machine_get_revb(Object *obj, Error **errp) +{ + SiFiveEState *s =3D RISCV_E_MACHINE(obj); + + return s->revb; +} + +static void sifive_e_machine_set_revb(Object *obj, bool value, Error **err= p) +{ + SiFiveEState *s =3D RISCV_E_MACHINE(obj); + + s->revb =3D value; +} + static void sifive_e_machine_instance_init(Object *obj) { + SiFiveEState *s =3D RISCV_E_MACHINE(obj); + + s->revb =3D false; + object_property_add_bool(obj, "revb", sifive_e_machine_get_revb, + sifive_e_machine_set_revb, NULL); + object_property_set_description(obj, "revb", + "Set on to tell QEMU that it should mo= del " + "the revB HiFive1 board", + NULL); } =20 static void sifive_e_machine_class_init(ObjectClass *oc, void *data) --=20 2.26.2