From nobody Sun Apr 12 07:36:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1775960555; cv=none; d=zohomail.com; s=zohoarc; b=gaBpEtQsVgdY8bp/ezTSvdKLIZvSZPwjdMDZlQAVTb0+JK1mKmbL5lcLoVUl2x4GdlyEWjgZl2cnXJ+hJ7gw6C1MIN/ZMSsOQNcwJ/Q8C+rVZ6RWSVr9Km6xYjjQHpARs6IuUkXGDNlBcqjV2y5cDTdZn520cmHuHL33emLB/ZE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1775960555; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=r4TyZefY9NFwD1+f8ide9sGoKm39GlSzIyT0VGj0ISI=; b=LP7yanmwL1eeXpJzTNnRiXLWPQ2nC3E3lR4BeKgMQhhK+Ef38ULMOeq/JCqHWX4sZS3vICVJz9TtLi2XrQ/+sy0cIm1w/EKg1TbBLGV6HgFuXjPrwZxSB7RakVQai/VsPOSLc2Qs/AIiliRWOUZByVVoOPZfTvcZt4bvABvYNGU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1775960555224827.0489697757861; Sat, 11 Apr 2026 19:22:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists1p.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1wBkRn-0004B8-UW; Sat, 11 Apr 2026 22:21:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1wBkRl-0004Ae-KU for qemu-devel@nongnu.org; Sat, 11 Apr 2026 22:21:13 -0400 Received: from mail-qv1-xf43.google.com ([2607:f8b0:4864:20::f43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1wBkRj-0008FP-M6 for qemu-devel@nongnu.org; Sat, 11 Apr 2026 22:21:13 -0400 Received: by mail-qv1-xf43.google.com with SMTP id 6a1803df08f44-8a1e1817db6so28502546d6.2 for ; Sat, 11 Apr 2026 19:21:11 -0700 (PDT) Received: from ZEVORN-PC.bbrouter ([162.244.208.119]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8aca05592ecsm15455576d6.29.2026.04.11.19.21.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Apr 2026 19:21:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1775960471; x=1776565271; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r4TyZefY9NFwD1+f8ide9sGoKm39GlSzIyT0VGj0ISI=; b=tGR+cNuiqwInExOc6KWoKPguozWozJB3pO6TsIkkq6ztHyoQUpH+13E9pQmxrFzCd1 usPBr2Ou5fvvwFL+wENqbiq0SrPCPcUdqvC2za+N7SMFpaIQlETbClh/oRXfe42JpIun n0nuCmUJllypww8NcdM9RB7s88uoV/TFoxLiHLXGCV+1ZyNW1gEVJikmxo6mQvWsiL3C EAx8ofw6CjUDDjF/uoYBUKZmwcACNZMQZDg7wGPjI6wHmW5NbV2kFFiMEtTsdGryu+le 4ekB/WGP9g7WTpCQSvkbC3xm14tXwQItwAI59sSbDQD/8mEvauDm7o7CFSKbVSVmYdUg dOJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1775960471; x=1776565271; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=r4TyZefY9NFwD1+f8ide9sGoKm39GlSzIyT0VGj0ISI=; b=HreLh32IWRt7MS6EekHZWWaMp+7qAK6BkDzqE8rxT+Oq0v+9+xE9Dv59KPkJqfWg9H iLSEPcana7ds7cCGqkQHTTHZ1x/aRCeibyAtN42C0lJyXaCwFNjOvxrOEs+KbQ2AbfRx XlzSjTT7fFI7E8M/DiiyRV3MKEIxsPJW8I/Ip+ld+hMbjxcFiWlKeuf1C0PI8R0Hqimq Kl0B4q+pGsEd7NEMBHugOHX+FDUSfRYcpz6bonPlzr7sP3yUefkOv+zUpCSszJSzZ98n 8WW2T/hs9eZf8fga9EXPJ5myzov5fUzKLbDodeR5nC8nFsXYfGwN3SpibMn7bAv8ljCj B80g== X-Gm-Message-State: AOJu0YzAnANg6cwz7arB7od6KSkUaHo48iZ205RcbI+R55zwV9LqDVPL lmeYkfLKgjPe/6UcaUgr54CtGpZbQmnMnMpWY72YNmhyxGjY4l7X0ITciSjWFDOHKQKdJioy X-Gm-Gg: AeBDieucV965Skbc5SwSRWGEdD8u7iaTIZxHOQTvDhuTFGNxJ5ZL3CINdvCfmpqC9+O 8lLUjFCOOREcR/pJA7RTCUmqaEO6MIym9Ps9szGG11L3shR+kFIJIOiOTQhhplhEXzIv0an3eoI 2BXqx0BlwsnuijeZb46QMiPsdzgd/HpVc+6NwaiTjwkZ2iyjp8+5CqEydxWDvJPeE+9mvqf+Uyc LffFLApjCRzHJTm8oa+ZNSWkzWn/+TJPDw11a2pwVywLJM9v5+djxk5uzKa75+8UdiW1uTJsGje dj/beM6N3TkdIL51/d72LnHuYM0dx0gMG0QkYf7yqgB6rH/dKQjgk7YdfqZslUvk4S98BMF7/XI mjc1JW0sv2pHZ4GruczjcdfATZtsHvBSIsPkIAuswiSNxnN8glsu17HWCsJagqaf4dF9vKlRRYl H5AMnuI3+Z/3D0Jy0CqSbvh3xb5SdGpWDlRbcTZ+FxWJLP5RFEdm0FOAE0ccAuaavm5fJNW6dvn w7K3lc= X-Received: by 2002:ad4:4ea7:0:b0:89c:9fa2:5de9 with SMTP id 6a1803df08f44-8ac862a63dbmr150577846d6.36.1775960470682; Sat, 11 Apr 2026 19:21:10 -0700 (PDT) From: Chao Liu To: Pierrick Bouvier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu Cc: qemu-devel@nongnu.org, tangtao1634@phytium.com.cn, devel@lists.libvirt.org, qemu-riscv@nongnu.org Subject: [PATCH v6 1/7] target/riscv: deprecate 'debug' CPU property Date: Sun, 12 Apr 2026 10:20:18 +0800 Message-ID: <99f0437cbb0169ffa318af4864ee48af22abeb17.1775959096.git.chao.liu.zevorn@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists1p.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f43; envelope-from=chao.liu.zevorn@gmail.com; helo=mail-qv1-xf43.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1775960555535158500 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza Starting on commit f31ba686a9 ("target/riscv/cpu.c: add 'sdtrig' in riscv,isa') the 'debug' flag has been used as an alias for 'sdtrig'. We're going to add more debug trigger extensions, e.g. 'sdext' [1]. And all of a sudden the existence of this flag is now weird. Do we keep it as a 'sdtrig' only or do we add 'sdext'? The solution proposed here is to deprecate it. The flag was introduced a long time ago as a way to encapsulate support for all debug related CSRs. Today we have specific debug trigger extensions and there's no more use for a generic 'debug' flag. Users should be encouraged to enable/disable extensions directly instead of using "made-up" flags that exists only in a QEMU context. The following changes are made: - 'ext_sdtrig' flag was added in cpu->cfg. 'debug' flag was removed from cpu->cfg; - All occurrences of cpu->cfg.debug were replaced to 'ext_sdtrig'; - Two explicit getters and setters for the 'debug' property were added. The property will simply get/set ext_sdtrig; - vmstate_debug was renamed to vmstate_sdtrig. We're aware that this will impact migration between QEMU 10.2 to newer versions, but we're still in a point where the migration break cost isn't big enough to justify adding migration compatibility scaffolding. Finally, deprecated.rst was updated to deprecate 'debug' and encourage users to use 'ext_sdtrig' instead. [1] https://lore.kernel.org/qemu-devel/cover.1768622881.git.chao.liu.zevorn= @gmail.com/ Signed-off-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Tested-by: Tao Tang --- docs/about/deprecated.rst | 7 +++++ target/riscv/cpu.c | 51 ++++++++++++++++++++++++++++--- target/riscv/cpu_cfg_fields.h.inc | 2 +- target/riscv/csr.c | 2 +- target/riscv/machine.c | 24 +++++++-------- target/riscv/tcg/tcg-cpu.c | 2 +- 6 files changed, 69 insertions(+), 19 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index a6d6a71326..cba050334b 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -452,6 +452,13 @@ It was implemented as a no-op instruction in TCG up to= QEMU 9.0, but only with ``-cpu max`` (which does not guarantee migration compatibility across versions). =20 +``debug=3Dtrue|false`` on RISC-V CPUs (since 11.0) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +This option, since QEMU 10.1, has been a simple alias to the ``sdtrig`` +extension. Users are advised to enable/disable ``sdtrig`` directly instead +of using ``debug``. + Backwards compatibility ----------------------- =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 38286b6b40..6208201538 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -210,7 +210,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), - ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, debug), + ISA_EXT_DATA_ENTRY(sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), ISA_EXT_DATA_ENTRY(shcounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sha, PRIV_VERSION_1_12_0, ext_sha), ISA_EXT_DATA_ENTRY(shgatpa, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -783,7 +783,7 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType= type) env->vill =3D true; =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.ext_sdtrig) { riscv_trigger_reset_hold(env); } =20 @@ -947,7 +947,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) riscv_cpu_register_gdb_regs_for_features(cs); =20 #ifndef CONFIG_USER_ONLY - if (cpu->cfg.debug) { + if (cpu->cfg.ext_sdtrig) { riscv_trigger_realize(&cpu->env); } #endif @@ -1126,6 +1126,14 @@ static void riscv_cpu_init(Object *obj) cpu->env.vext_ver =3D VEXT_VERSION_1_00_0; cpu->cfg.max_satp_mode =3D -1; =20 + /* + * 'debug' started being deprecated in 11.0, been just a proxy + * to set ext_sdtrig ever since. It has been enabled by default + * for a long time though, so we're stuck with setting set 'strig' + * by default too. At least for now ... + */ + cpu->cfg.ext_sdtrig =3D true; + if (mcc->def->profile) { mcc->def->profile->enabled =3D true; } @@ -1240,6 +1248,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = =3D { MULTI_EXT_CFG_BOOL("smcdeleg", ext_smcdeleg, false), MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false), MULTI_EXT_CFG_BOOL("ssccfg", ext_ssccfg, false), + MULTI_EXT_CFG_BOOL("sdtrig", ext_sdtrig, true), MULTI_EXT_CFG_BOOL("smctr", ext_smctr, false), MULTI_EXT_CFG_BOOL("ssctr", ext_ssctr, false), MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), @@ -2654,8 +2663,42 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rul= es[] =3D { NULL }; =20 +/* + * DEPRECATED_11.0: just a proxy for ext_sdtrig. + */ +static void prop_debug_get(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool value =3D RISCV_CPU(obj)->cfg.ext_sdtrig; + + visit_type_bool(v, name, &value, errp); +} + +/* + * DEPRECATED_11.0: just a proxy for ext_sdtrig. + */ +static void prop_debug_set(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + bool value; + + visit_type_bool(v, name, &value, errp); + cpu->cfg.ext_sdtrig =3D value; +} + +/* + * DEPRECATED_11.0: just a proxy for ext_sdtrig. + */ +static const PropertyInfo prop_debug =3D { + .type =3D "bool", + .description =3D "DEPRECATED: use 'sdtrig' instead.", + .get =3D prop_debug_get, + .set =3D prop_debug_set, +}; + static const Property riscv_cpu_properties[] =3D { - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + {.name =3D "debug", .info =3D &prop_debug}, =20 {.name =3D "pmu-mask", .info =3D &prop_pmu_mask}, {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 734fa079f2..44235bfaa1 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -46,6 +46,7 @@ BOOL_FIELD(ext_zilsd) BOOL_FIELD(ext_zimop) BOOL_FIELD(ext_zcmop) BOOL_FIELD(ext_ztso) +BOOL_FIELD(ext_sdtrig) BOOL_FIELD(ext_smstateen) BOOL_FIELD(ext_sstc) BOOL_FIELD(ext_smcdeleg) @@ -159,7 +160,6 @@ BOOL_FIELD(ext_xlrbr) =20 BOOL_FIELD(mmu) BOOL_FIELD(pmp) -BOOL_FIELD(debug) BOOL_FIELD(misa_w) =20 BOOL_FIELD(short_isa_string) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index cfd076b368..93b4864933 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -776,7 +776,7 @@ static RISCVException have_mseccfg(CPURISCVState *env, = int csrno) =20 static RISCVException debug(CPURISCVState *env, int csrno) { - if (riscv_cpu_cfg(env)->debug) { + if (riscv_cpu_cfg(env)->ext_sdtrig) { return RISCV_EXCP_NONE; } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 09c032a879..62c51c8033 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -218,14 +218,14 @@ static const VMStateDescription vmstate_kvmtimer =3D { }; #endif =20 -static bool debug_needed(void *opaque) +static bool sdtrig_needed(void *opaque) { RISCVCPU *cpu =3D opaque; =20 - return cpu->cfg.debug; + return cpu->cfg.ext_sdtrig; } =20 -static int debug_post_load(void *opaque, int version_id) +static int sdtrig_post_load(void *opaque, int version_id) { RISCVCPU *cpu =3D opaque; CPURISCVState *env =3D &cpu->env; @@ -237,12 +237,12 @@ static int debug_post_load(void *opaque, int version_= id) return 0; } =20 -static const VMStateDescription vmstate_debug =3D { - .name =3D "cpu/debug", - .version_id =3D 2, - .minimum_version_id =3D 2, - .needed =3D debug_needed, - .post_load =3D debug_post_load, +static const VMStateDescription vmstate_sdtrig =3D { + .name =3D "cpu/sdtrig", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D sdtrig_needed, + .post_load =3D sdtrig_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), @@ -425,8 +425,8 @@ static const VMStateDescription vmstate_sstc =3D { =20 const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", - .version_id =3D 11, - .minimum_version_id =3D 11, + .version_id =3D 12, + .minimum_version_id =3D 12, .post_load =3D riscv_cpu_post_load, .fields =3D (const VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32), @@ -492,13 +492,13 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_kvmtimer, #endif &vmstate_envcfg, - &vmstate_debug, &vmstate_smstateen, &vmstate_jvt, &vmstate_elp, &vmstate_ssp, &vmstate_ctr, &vmstate_sstc, + &vmstate_sdtrig, NULL } }; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index f3f7808895..0613450691 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -180,7 +180,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) ? EXT_STATUS_DIRTY : EXT_STATUS_DISABLED; } =20 - if (cpu->cfg.debug && !icount_enabled()) { + if (cpu->cfg.ext_sdtrig && !icount_enabled()) { flags =3D FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enab= led); } #endif --=20 2.53.0