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charset="utf-8" Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu_bits.h | 11 ++++ target/riscv/csr.c | 119 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 130 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 162d42f211..95909f159a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -191,6 +191,17 @@ #define HGATP_PPN SATP64_PPN #endif =20 +/* Virtual CSRs */ +#define CSR_VSSTATUS 0x200 +#define CSR_VSIE 0x204 +#define CSR_VSTVEC 0x205 +#define CSR_VSSCRATCH 0x240 +#define CSR_VSEPC 0x241 +#define CSR_VSCAUSE 0x242 +#define CSR_VSTVAL 0x243 +#define CSR_VSIP 0x244 +#define CSR_VSATP 0x280 + /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index edfafca06f..a1eb15f507 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -817,6 +817,115 @@ static int write_hgatp(CPURISCVState *env, int csrno,= target_ulong val) return 0; } =20 +/* Virtual CSR Registers */ +static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vsstatus; + return 0; +} + +static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsstatus =3D val; + return 0; +} + +static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vsie; + return 0; +} + +static int write_vsie(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsie =3D val; + return 0; +} + +static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vstvec; + return 0; +} + +static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vstvec =3D val; + return 0; +} + +static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vsscratch; + return 0; +} + +static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsscratch =3D val; + return 0; +} + +static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vsepc; + return 0; +} + +static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsepc =3D val; + return 0; +} + +static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vscause; + return 0; +} + +static int write_vscause(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vscause =3D val; + return 0; +} + +static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vstval; + return 0; +} + +static int write_vstval(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vstval =3D val; + return 0; +} + +static int read_vsip(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D (target_ulong)atomic_read(&env->vsip); + return 0; +} + +static int write_vsip(CPURISCVState *env, int csrno, target_ulong val) +{ + atomic_set(&env->vsip, val); + return 0; +} + +static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vsatp; + return 0; +} + +static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vsatp =3D val; + return 0; +} + /* Physical Memory Protection */ static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1025,6 +1134,16 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_HIDELEG] =3D { hmode, read_hideleg, write_hidel= eg }, [CSR_HGATP] =3D { hmode, read_hgatp, write_hgatp= }, =20 + [CSR_VSSTATUS] =3D { hmode, read_vsstatus, write_vssta= tus }, + [CSR_VSIE] =3D { hmode, read_vsie, write_vsie = }, + [CSR_VSTVEC] =3D { hmode, read_vstvec, write_vstve= c }, + [CSR_VSSCRATCH] =3D { hmode, read_vsscratch, write_vsscr= atch }, + [CSR_VSEPC] =3D { hmode, read_vsepc, write_vsepc= }, + [CSR_VSCAUSE] =3D { hmode, read_vscause, write_vscau= se }, + [CSR_VSTVAL] =3D { hmode, read_vstval, write_vstva= l }, + [CSR_VSIP] =3D { hmode, read_vsip, write_vsip = }, + [CSR_VSATP] =3D { hmode, read_vsatp, write_vsatp= }, + /* Physical Memory Protection */ [CSR_PMPCFG0 ... CSR_PMPADDR9] =3D { pmp, read_pmpcfg, write_pmpc= fg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] =3D { pmp, read_pmpaddr, write_pmpa= ddr }, --=20 2.23.0