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X-Received-From: 68.232.141.245 Subject: [Qemu-devel] [PATCH for 4.1 v2 2/6] target/riscv: Fall back to generating a RISC-V CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "alistair23@gmail.com" , "palmer@sifive.com" , Alistair Francis Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) Content-Type: text/plain; charset="utf-8" If a user specifies a CPU that we don't understand then we want to fall back to a CPU generated from the ISA string. At the moment the generated CPU is assumed to be a privledge spec version 1.10 CPU with an MMU. This can be changed in the future. Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 95 +++++++++++++++++++++++++++++++++++++++++++++- target/riscv/cpu.h | 2 + 2 files changed, 96 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d61bce6d55..31561c719f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "cpu.h" #include "exec/exec-all.h" #include "qapi/error.h" @@ -103,6 +104,93 @@ static void set_resetvec(CPURISCVState *env, int reset= vec) #endif } =20 +static void riscv_generate_cpu_init(Object *obj) +{ + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + const char *riscv_cpu =3D mcc->isa_str; + target_ulong target_misa =3D 0; + target_ulong rvxlen =3D 0; + int i; + bool valid =3D false; + + for (i =3D 0; i < strlen(riscv_cpu); i++) { + if (i =3D=3D 0 && riscv_cpu[i] =3D=3D 'r' && + riscv_cpu[i + 1] =3D=3D 'v') { + /* Starts with "rv" */ + i +=3D 2; + if (riscv_cpu[i] =3D=3D '3' && riscv_cpu[i + 1] =3D=3D '2') { + i +=3D 2; + valid =3D true; + rvxlen =3D RV32; + } + if (riscv_cpu[i] =3D=3D '6' && riscv_cpu[i + 1] =3D=3D '4') { + i +=3D 2; + valid =3D true; + rvxlen =3D RV64; + } + } + + switch (riscv_cpu[i]) { + case 'i': + if (target_misa & RVE) { + error_report("I and E extensions are incompatible"); + exit(1); + } + target_misa |=3D RVI; + continue; + case 'e': + if (target_misa & RVI) { + error_report("I and E extensions are incompatible"); + exit(1); + } + target_misa |=3D RVE; + continue; + case 'g': + target_misa |=3D RVI | RVM | RVA | RVF | RVD; + continue; + case 'm': + target_misa |=3D RVM; + continue; + case 'a': + target_misa |=3D RVA; + continue; + case 'f': + target_misa |=3D RVF; + continue; + case 'd': + target_misa |=3D RVD; + continue; + case 'c': + target_misa |=3D RVC; + continue; + case 's': + target_misa |=3D RVS; + continue; + case 'u': + target_misa |=3D RVU; + continue; + default: + warn_report("QEMU does not support the %c extension", + riscv_cpu[i]); + continue; + } + } + + if (!valid) { + error_report("'%s' does not appear to be a valid RISC-V CPU", + riscv_cpu); + exit(1); + } + + set_misa(env, rvxlen | target_misa); + set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); + set_feature(env, RISCV_FEATURE_MMU); + set_feature(env, RISCV_FEATURE_PMP); +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; @@ -178,6 +266,7 @@ static void rv64imacu_nommu_cpu_init(Object *obj) static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) { ObjectClass *oc; + RISCVCPUClass *mcc; char *typename; char **cpuname; =20 @@ -188,7 +277,10 @@ static ObjectClass *riscv_cpu_class_by_name(const char= *cpu_model) g_free(typename); if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || object_class_is_abstract(oc)) { - return NULL; + /* No CPU found, try the generic CPU and pass in the ISA string */ + oc =3D object_class_by_name(TYPE_RISCV_CPU_GEN); + mcc =3D RISCV_CPU_CLASS(oc); + mcc->isa_str =3D g_strdup(cpu_model); } return oc; } @@ -440,6 +532,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { .class_init =3D riscv_cpu_class_init, }, DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_GEN, riscv_generate_cpu_init), #if defined(TARGET_RISCV32) DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_in= it), DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_in= it), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 20bce8742e..453108a855 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -48,6 +48,7 @@ #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU =20 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_GEN RISCV_CPU_TYPE_NAME("rv*") #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9= .1") #define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.1= 0.0") #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nom= mu") @@ -211,6 +212,7 @@ typedef struct RISCVCPUClass { /*< public >*/ DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + const char *isa_str; } RISCVCPUClass; =20 /** --=20 2.21.0