From nobody Sun Nov 24 05:27:37 2024 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D460A78297 for ; Sat, 14 Sep 2024 06:13:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726294434; cv=none; b=ko+xn+nuQ/EOAKUD572a/P3oO+Uzz/DGvNuKzF4lt2Sp67l0sy46mB7nUkRhfUOZT4rQ8tm03ghuVJrEsyAbdfDICTQzlac/camXwQ7VXwkCIGNnOaRf9tVgCz7yGKHZ0m/QTYnioxjdOu8OuW4EcH4tBRAXbwWX4O2z3RaiEys= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726294434; c=relaxed/simple; bh=3f3lYse//dJA0XEP5BXOBK6woRI3WzPY7s6X6axPSWI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qH01nZo2NAsfghm3aNewp+7vPuQsUiOrj+dAMBp0M62a67Fi/+B2qQtGEM/Ku+Cb+2XwQw5dTCyEq+avOYz5ZqBft1BwhB9Npai4+4nWUK1HZyeBjwhiOCTHU6f7ybGsFqq8wa4+kPeTj56UbRKgxs+ERSfnWf3NmljfZ1DYPxw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jhNeBorH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jhNeBorH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D35EC4CEE9; Sat, 14 Sep 2024 06:13:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1726294434; bh=3f3lYse//dJA0XEP5BXOBK6woRI3WzPY7s6X6axPSWI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jhNeBorHB3gQ1iRRhCOZx1c6uRZxDQzwBOZouQ5Jtjbbg6vSzSJmm0vge7IuyCji4 jZnvpq9hP5SiO9UK2cy2QGOm+DUS2L+T9shWbI9Kf8Lr6GVMsvjh3vL85FnlPabLu9 xEzpaivFYNucZJyT2jkYIgW/yFiJfNA8vO0a8+RIjnE2LS/qeL4kPe1f8lHyACiT89 kFDo52oQOCmToG0bcCisxjeci103aadN1EFzrGIWPShJ68+sfHL/9lJIZlB3ZP6zxm bvuNHfz05GhhifL6P+lGA331tHcfmDQScV+nAlQpCyJqJzlXQ1FEGl2v6r0SjpvmB+ zVkITObcu4Ucg== Received: from mchehab by mail.kernel.org with local (Exim 4.98) (envelope-from ) id 1spM2a-00000003V6h-1wf9; Sat, 14 Sep 2024 08:13:52 +0200 From: Mauro Carvalho Chehab To: Igor Mammedov Cc: Jonathan Cameron , Shiju Jose , Mauro Carvalho Chehab , Peter Maydell , linux-kernel@vger.kernel.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v10 20/21] target/arm: add an experimental mpidr arm cpu property object Date: Sat, 14 Sep 2024 08:13:41 +0200 Message-ID: <98ed2f01cb2bdeb44b241fd36531b9e434fe6f52.1726293808.git.mchehab+huawei@kernel.org> X-Mailer: git-send-email 2.46.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: Mauro Carvalho Chehab Content-Type: text/plain; charset="utf-8" Accurately injecting an ARM Processor error ACPI/APEI GHES error record requires the value of the ARM Multiprocessor Affinity Register (mpidr). While ARM implements it, this is currently not visible. Add a field at CPU storing it, and place it at arm_cpu_properties as experimental, thus allowing it to be queried via QMP using qom-get function. Signed-off-by: Mauro Carvalho Chehab --- target/arm/cpu.c | 1 + target/arm/cpu.h | 1 + target/arm/helper.c | 10 ++++++++-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 19191c239181..30fcf0a10f46 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2619,6 +2619,7 @@ static ObjectClass *arm_cpu_class_by_name(const char = *cpu_model) =20 static Property arm_cpu_properties[] =3D { DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), + DEFINE_PROP_UINT64("x-mpidr", ARMCPU, mpidr, 0), DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, ARM64_AFFINITY_INVALID), DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f065756c5c7d..bf8e5943af4f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1033,6 +1033,7 @@ struct ArchCPU { uint64_t reset_pmcr_el0; } isar; uint64_t midr; + uint64_t mpidr; uint32_t revidr; uint32_t reset_fpsid; uint64_t ctr; diff --git a/target/arm/helper.c b/target/arm/helper.c index 0a582c1cd3b3..d6e7aa069489 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4690,7 +4690,7 @@ static uint64_t mpidr_read_val(CPUARMState *env) return mpidr; } =20 -static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) +static uint64_t mpidr_read(CPUARMState *env) { unsigned int cur_el =3D arm_current_el(env); =20 @@ -4700,6 +4700,11 @@ static uint64_t mpidr_read(CPUARMState *env, const A= RMCPRegInfo *ri) return mpidr_read_val(env); } =20 +static uint64_t mpidr_read_ri(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return mpidr_read(env); +} + static const ARMCPRegInfo lpae_cp_reginfo[] =3D { /* NOP AMAIR0/1 */ { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, @@ -9721,7 +9726,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "MPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D = 5, .fgt =3D FGT_MPIDR_EL1, - .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, + .access =3D PL1_R, .readfn =3D mpidr_read_ri, .type =3D ARM_= CP_NO_RAW }, }; #ifdef CONFIG_USER_ONLY static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { @@ -9731,6 +9736,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); #endif define_arm_cp_regs(cpu, mpidr_cp_reginfo); + cpu->mpidr =3D mpidr_read(env); } =20 if (arm_feature(env, ARM_FEATURE_AUXCR)) { --=20 2.46.0