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charset="utf-8" Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 13 +++++- target/riscv/cpu_bits.h | 7 ++++ target/riscv/cpu_helper.c | 88 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 107 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5b71ee416f..0ea56f9059 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -125,6 +125,8 @@ struct CPURISCVState { target_ulong *mstatus; =20 target_ulong mip; + target_ulong mip_novirt; + uint32_t miclaim; =20 target_ulong *mie; @@ -161,7 +163,7 @@ struct CPURISCVState { =20 /* Virtual CSRs */ target_ulong vsstatus; - uint32_t vsip; + target_ulong vsip; target_ulong vsie; target_ulong vstvec; target_ulong vsscratch; @@ -170,6 +172,14 @@ struct CPURISCVState { target_ulong vstval; target_ulong vsatp; =20 + /* HS Backup CSRs */ + target_ulong stvec_hs; + target_ulong sscratch_hs; + target_ulong sepc_hs; + target_ulong scause_hs; + target_ulong stval_hs; + target_ulong satp_hs; + target_ulong scounteren; target_ulong mcounteren; =20 @@ -300,6 +310,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 95909f159a..d66a29bdb1 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -553,4 +553,11 @@ #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP =20 +/* MIE masks */ +#define MIE_SEIE (1 << IRQ_S_EXT) +#define MIE_UEIE (1 << IRQ_U_EXT) +#define MIE_STIE (1 << IRQ_S_TIMER) +#define MIE_UTIE (1 << IRQ_U_TIMER) +#define MIE_SSIE (1 << IRQ_S_SOFT) +#define MIE_USIE (1 << IRQ_U_SOFT) #endif diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 21d049cdce..12a10e8679 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -82,6 +82,94 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } =20 +void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) +{ + RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + uint32_t tmp; + target_ulong mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | + MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE; + target_ulong sie_mask =3D MIE_SEIE | MIE_STIE | MIE_SSIE | + MIE_UEIE | MIE_UTIE | MIE_USIE; + target_ulong mip_mask =3D MIP_SSIP | MIP_STIP | MIP_SEIP; + bool current_virt =3D riscv_cpu_virt_enabled(env); + + g_assert(riscv_has_ext(env, RVH)); + +#if defined(TARGET_RISCV64) + mstatus_mask |=3D MSTATUS64_UXL; +#endif + + if (current_virt) { + /* Current V=3D1 and we are about to change to V=3D0 */ + env->mstatus =3D &env->mstatus_novirt; + *env->mstatus &=3D mstatus_mask; + *env->mstatus |=3D env->vsstatus & ~mstatus_mask; + /* Ensure that vsstatus only holds the correct bits */ + env->vsstatus &=3D mstatus_mask; + + env->mie =3D &env->mie_novirt; + *env->mie &=3D sie_mask; + *env->mie |=3D env->vsie & ~sie_mask; + /* Ensure that vsie only holds the correct bits */ + env->vsie &=3D sie_mask; + + env->vstvec =3D env->stvec; + env->stvec =3D env->stvec_hs; + + env->vsscratch =3D env->sscratch; + env->sscratch =3D env->sscratch_hs; + + env->vsepc =3D env->sepc; + env->sepc =3D env->sepc_hs; + + env->vscause =3D env->scause; + env->scause =3D env->scause_hs; + + env->vstval =3D env->sbadaddr; + env->sbadaddr =3D env->stval_hs; + + env->vsatp =3D env->satp; + env->satp =3D env->satp_hs; + + tmp =3D env->mip_novirt; + tmp =3D riscv_cpu_update_mip(cpu, mip_mask, tmp); + tmp &=3D mip_mask; + env->vsip =3D tmp; + } else { + /* Current V=3D0 and we are about to change to V=3D1 */ + env->mstatus =3D &env->vsstatus; + *env->mstatus &=3D mstatus_mask; + *env->mstatus |=3D env->mstatus_novirt & ~mstatus_mask; + + env->mie =3D &env->vsie; + *env->mie &=3D sie_mask; + *env->mie |=3D env->mie_novirt & ~sie_mask; + + env->stvec_hs =3D env->stvec; + env->stvec =3D env->vstvec; + + env->sscratch_hs =3D env->sscratch; + env->sscratch =3D env->vsscratch; + + env->sepc_hs =3D env->sepc; + env->sepc =3D env->vsepc; + + env->scause_hs =3D env->scause; + env->scause =3D env->vscause; + + env->stval_hs =3D env->sbadaddr; + env->sbadaddr =3D env->vstval; + + env->satp_hs =3D env->satp; + env->satp =3D env->vsatp; + + tmp =3D env->vsip; + tmp =3D riscv_cpu_update_mip(cpu, mip_mask, tmp); + tmp &=3D mip_mask; + env->mip_novirt =3D tmp; + } +} + bool riscv_cpu_virt_enabled(CPURISCVState *env) { if (!riscv_has_ext(env, RVH)) { --=20 2.23.0