From nobody Wed Nov 5 15:47:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zoho.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 149727600429986.46837049866872; Mon, 12 Jun 2017 07:00:04 -0700 (PDT) Received: from localhost ([::1]:38214 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKPsv-0000Mn-Tq for importer@patchew.org; Mon, 12 Jun 2017 10:00:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39491) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKPjq-0000qK-1i for qemu-devel@nongnu.org; Mon, 12 Jun 2017 09:50:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dKPjo-0008Qr-I0 for qemu-devel@nongnu.org; Mon, 12 Jun 2017 09:50:38 -0400 Received: from [59.151.112.132] (port=55865 helo=heian.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dKPjn-0008Q5-JB for qemu-devel@nongnu.org; Mon, 12 Jun 2017 09:50:36 -0400 Received: from unknown (HELO cn.fujitsu.com) ([10.167.33.5]) by heian.cn.fujitsu.com with ESMTP; 12 Jun 2017 21:50:24 +0800 Received: from G08CNEXCHPEKD02.g08.fujitsu.local (unknown [10.167.33.83]) by cn.fujitsu.com (Postfix) with ESMTP id D11D447C7C85; Mon, 12 Jun 2017 21:50:24 +0800 (CST) Received: from maozy.g08.fujitsu.local (10.167.225.76) by G08CNEXCHPEKD02.g08.fujitsu.local (10.167.33.89) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 12 Jun 2017 21:50:24 +0800 X-IronPort-AV: E=Sophos;i="5.22,518,1449504000"; d="scan'208";a="19936597" From: Mao Zhongyi To: Date: Mon, 12 Jun 2017 21:48:31 +0800 Message-ID: <95d084fb4115896b8d2d89aa44f8b817026dcc57.1497272778.git.maozy.fnst@cn.fujitsu.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.167.225.76] X-yoursite-MailScanner-ID: D11D447C7C85.A3744 X-yoursite-MailScanner: Found to be clean X-yoursite-MailScanner-From: maozy.fnst@cn.fujitsu.com X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 59.151.112.132 Subject: [Qemu-devel] [PATCH v5 5/9] pci: Replace pci_add_capability2() with pci_add_capability() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, armbru@redhat.com, marcel@redhat.com, alex.williamson@redhat.com, dmitry@daynix.com, pbonzini@redhat.com, rth@twiddle.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" After the patch 'Make errp the last parameter of pci_add_capability()', pci_add_capability() and pci_add_capability2() now do exactly the same. So drop the wrapper pci_add_capability() of pci_add_capability2(), then replace the pci_add_capability2() with pci_add_capability() everywhere. Cc: pbonzini@redhat.com Cc: rth@twiddle.net Cc: ehabkost@redhat.com Cc: mst@redhat.com Cc: dmitry@daynix.com Cc: jasowang@redhat.com Cc: marcel@redhat.com Cc: alex.williamson@redhat.com Cc: armbru@redhat.com Suggested-by: Eduardo Habkost Signed-off-by: Mao Zhongyi --- hw/i386/kvm/pci-assign.c | 14 +++++++------- hw/ide/ich.c | 2 +- hw/pci/msi.c | 2 +- hw/pci/msix.c | 2 +- hw/pci/pci.c | 20 ++------------------ hw/vfio/pci.c | 6 +++--- include/hw/pci/pci.h | 3 --- 7 files changed, 15 insertions(+), 34 deletions(-) diff --git a/hw/i386/kvm/pci-assign.c b/hw/i386/kvm/pci-assign.c index 87dcbdd..3d60455 100644 --- a/hw/i386/kvm/pci-assign.c +++ b/hw/i386/kvm/pci-assign.c @@ -1254,7 +1254,7 @@ static int assigned_device_pci_cap_init(PCIDevice *pc= i_dev, Error **errp) dev->dev.cap_present |=3D QEMU_PCI_CAP_MSI; dev->cap.available |=3D ASSIGNED_DEVICE_CAP_MSI; /* Only 32-bit/no-mask currently supported */ - ret =3D pci_add_capability2(pci_dev, PCI_CAP_ID_MSI, pos, 10, + ret =3D pci_add_capability(pci_dev, PCI_CAP_ID_MSI, pos, 10, &local_err); if (ret < 0) { error_propagate(errp, local_err); @@ -1288,7 +1288,7 @@ static int assigned_device_pci_cap_init(PCIDevice *pc= i_dev, Error **errp) } dev->dev.cap_present |=3D QEMU_PCI_CAP_MSIX; dev->cap.available |=3D ASSIGNED_DEVICE_CAP_MSIX; - ret =3D pci_add_capability2(pci_dev, PCI_CAP_ID_MSIX, pos, 12, + ret =3D pci_add_capability(pci_dev, PCI_CAP_ID_MSIX, pos, 12, &local_err); if (ret < 0) { error_propagate(errp, local_err); @@ -1318,7 +1318,7 @@ static int assigned_device_pci_cap_init(PCIDevice *pc= i_dev, Error **errp) if (pos) { uint16_t pmc; =20 - ret =3D pci_add_capability2(pci_dev, PCI_CAP_ID_PM, pos, PCI_PM_SI= ZEOF, + ret =3D pci_add_capability(pci_dev, PCI_CAP_ID_PM, pos, PCI_PM_SIZ= EOF, &local_err); if (ret < 0) { error_propagate(errp, local_err); @@ -1386,7 +1386,7 @@ static int assigned_device_pci_cap_init(PCIDevice *pc= i_dev, Error **errp) return -EINVAL; } =20 - ret =3D pci_add_capability2(pci_dev, PCI_CAP_ID_EXP, pos, size, + ret =3D pci_add_capability(pci_dev, PCI_CAP_ID_EXP, pos, size, &local_err); if (ret < 0) { error_propagate(errp, local_err); @@ -1462,7 +1462,7 @@ static int assigned_device_pci_cap_init(PCIDevice *pc= i_dev, Error **errp) uint32_t status; =20 /* Only expose the minimum, 8 byte capability */ - ret =3D pci_add_capability2(pci_dev, PCI_CAP_ID_PCIX, pos, 8, + ret =3D pci_add_capability(pci_dev, PCI_CAP_ID_PCIX, pos, 8, &local_err); if (ret < 0) { error_propagate(errp, local_err); @@ -1490,7 +1490,7 @@ static int assigned_device_pci_cap_init(PCIDevice *pc= i_dev, Error **errp) pos =3D pci_find_cap_offset(pci_dev, PCI_CAP_ID_VPD, 0); if (pos) { /* Direct R/W passthrough */ - ret =3D pci_add_capability2(pci_dev, PCI_CAP_ID_VPD, pos, 8, + ret =3D pci_add_capability(pci_dev, PCI_CAP_ID_VPD, pos, 8, &local_err); if (ret < 0) { error_propagate(errp, local_err); @@ -1508,7 +1508,7 @@ static int assigned_device_pci_cap_init(PCIDevice *pc= i_dev, Error **errp) pos +=3D PCI_CAP_LIST_NEXT) { uint8_t len =3D pci_get_byte(pci_dev->config + pos + PCI_CAP_FLAGS= ); /* Direct R/W passthrough */ - ret =3D pci_add_capability2(pci_dev, PCI_CAP_ID_VNDR, pos, len, + ret =3D pci_add_capability(pci_dev, PCI_CAP_ID_VNDR, pos, len, &local_err); if (ret < 0) { error_propagate(errp, local_err); diff --git a/hw/ide/ich.c b/hw/ide/ich.c index 4599169..989fca5 100644 --- a/hw/ide/ich.c +++ b/hw/ide/ich.c @@ -130,7 +130,7 @@ static void pci_ich9_ahci_realize(PCIDevice *dev, Error= **errp) pci_register_bar(dev, ICH9_MEM_BAR, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->ahci.mem); =20 - sata_cap_offset =3D pci_add_capability2(dev, PCI_CAP_ID_SATA, + sata_cap_offset =3D pci_add_capability(dev, PCI_CAP_ID_SATA, ICH9_SATA_CAP_OFFSET, SATA_CAP_S= IZE, errp); if (sata_cap_offset < 0) { diff --git a/hw/pci/msi.c b/hw/pci/msi.c index a87b227..5e05ce5 100644 --- a/hw/pci/msi.c +++ b/hw/pci/msi.c @@ -216,7 +216,7 @@ int msi_init(struct PCIDevice *dev, uint8_t offset, } =20 cap_size =3D msi_cap_sizeof(flags); - config_offset =3D pci_add_capability2(dev, PCI_CAP_ID_MSI, offset, + config_offset =3D pci_add_capability(dev, PCI_CAP_ID_MSI, offset, cap_size, errp); if (config_offset < 0) { return config_offset; diff --git a/hw/pci/msix.c b/hw/pci/msix.c index bb54e8b..d634326 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -294,7 +294,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nen= tries, return -EINVAL; } =20 - cap =3D pci_add_capability2(dev, PCI_CAP_ID_MSIX, + cap =3D pci_add_capability(dev, PCI_CAP_ID_MSIX, cap_pos, MSIX_CAP_LENGTH, errp); if (cap < 0) { return cap; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 2bba37a..283ca5e 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2259,28 +2259,12 @@ static void pci_del_option_rom(PCIDevice *pdev) } =20 /* - * if offset =3D 0, - * Find and reserve space and add capability to the linked list - * in pci config space - */ -int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp) -{ - int ret; - - ret =3D pci_add_capability2(pdev, cap_id, offset, size, errp); - - return ret; -} - -/* - * On success, pci_add_capability2() returns a positive value + * On success, pci_add_capability() returns a positive value * that the offset of the pci capability. * On failure, it sets an error and returns a negative error * code. */ -int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, +int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t offset, uint8_t size, Error **errp) { diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 70bfb59..8de8272 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -1837,14 +1837,14 @@ static int vfio_add_std_cap(VFIOPCIDevice *vdev, ui= nt8_t pos, Error **errp) case PCI_CAP_ID_PM: vfio_check_pm_reset(vdev, pos); vdev->pm_cap =3D pos; - ret =3D pci_add_capability2(pdev, cap_id, pos, size, errp); + ret =3D pci_add_capability(pdev, cap_id, pos, size, errp); break; case PCI_CAP_ID_AF: vfio_check_af_flr(vdev, pos); - ret =3D pci_add_capability2(pdev, cap_id, pos, size, errp); + ret =3D pci_add_capability(pdev, cap_id, pos, size, errp); break; default: - ret =3D pci_add_capability2(pdev, cap_id, pos, size, errp); + ret =3D pci_add_capability(pdev, cap_id, pos, size, errp); break; } out: diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index fe52aa8..e598b09 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -358,9 +358,6 @@ pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int regio= n_num); int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t offset, uint8_t size, Error **errp); -int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id, - uint8_t offset, uint8_t size, - Error **errp); =20 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_si= ze); =20 --=20 2.9.3