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x=1600468165; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=B2gJ3AYtGJfxpiBCTCmZcHguxPxVbHMIn0H3NBT5lCc=; b=H8m0R2SIOj9lfUPDpWY315f8TKuMSUa3HnB2Xb01nFBUh+1n89SmFFgn sKuNfk8u2TIekTLWeQLGpbGEHUglnXtom5A2I5dsm1aJI46MCwaWfL03N ZHk+l+hJGM+jJSNsYES7XA6ohSLftyh5oAhWutZ9pB8wUNLDrJbYvb2ni z4BfwdsNKvp9ukmqI5TYtGfYqdjEDTEoGmZ47Mo7N8+eulObPYk4RZBJH 2fdKNoQR3moiERPls0dX7UuF3UE/n8Hd3mlOC95k4Is2WWdJMQqnNW7Rc T/oT96ObLYGO1BT6GVpJr8Z6G9283WN/CMeS1A6d223K2L9wyXtfKpqxa Q==; IronPort-SDR: BOFiuVx0rC55x8Dy7XB38bM5HQqUIXk37K9kFd+ga8JXz7TR47gXJXFgqk2iMcnKJlNG67f0ZD Q6suqSRP1B8+e3saJ0loxY3AVCf8B7fTfh57/k5+TFUaCLBTabEolvqqD6Fa/1wvYwxYWMS+nd N+RsMrMTqJBNZeE1OICoi+qHH3sZlh+IKu1/ggs18nFfLRYB+J1LTDG07pA1+48L8PCiRnZbYS 1rRrFNmEiLQpbsjnJHBFegmVwPFhINhL/5FzBU0BcRPPJF3hlXJ0TLphpbcjYoQhio3ViqaK92 zjg= X-IronPort-AV: E=Sophos;i="5.64,526,1559491200"; d="scan'208";a="219490590" IronPort-SDR: dknlNu4v2ne05JLeKaEV/m1AQPpApQxKj99nx4GBwLpBB5OnNMPs5fzMQepZ7J+lwYUi9VrWRD 9cw5SeymXOuPsw5U1eXM9YirZ1oQE5h/JSJVYpoSLsTrT+VkljjHnJq6vm/sBEWNGqmmY9TnwS 8gsRsA2An5z2ErI7zOAwsT/cIXEPU0e4aGtcZRx9SF53MWCyVEAyrPrJb10n8OJuKDxRYYVDHL GNw+Xt7fj6/CInagQfBZC7hxPX/dt0tDH1sZ+J2S0QGxPsHFvTTcisQpR1es3WHwODb+7L+UZ3 a9GRh4kB9aB7CXNSOQHyloaZ IronPort-SDR: phdgGjJsfcLJhzJUTi8ibtLU18q2CllfPiFfZkBEYzAq0SFXoATo3vKRxRtCPxdx39hPTp3iNF 9MQYdSa/Oxau6JqarwKYWNAeYUqErrqiBobpgrUenoChocoK85BoMnkUGyYJffcqb2rEFgo83x gC3b38vzaAZUT17ZVJ5STXXWR4GdehiafbwlY8MifFbkIHdnbhPKzxGG3xq6lrSj/2ml+UUjI3 /yYWFXsSGAb8Jc+Oc2ehLh1FnNakjgun/ZiWX4ZQmnYTLHCvDXB4iDWBQTHuIKHxr355uf/7NQ AbY= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v1 3/6] riscv/sifive_u: Manually define the machine Date: Thu, 19 Sep 2019 15:25:01 -0700 Message-Id: <95b47a08da3038df82cd1cc9d69cd005270906f8.1568931866.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 68.232.143.124 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to specify machine properties. This patch is no functional change. Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 27 +++++++++++++++++++++++---- include/hw/riscv/sifive_u.h | 7 ++++++- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9c5d791320..c3949fb316 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -310,8 +310,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, static void riscv_sifive_u_init(MachineState *machine) { const struct MemmapEntry *memmap =3D sifive_u_memmap; - - SiFiveUState *s =3D g_new0(SiFiveUState, 1); + SiFiveUState *s =3D RISCV_U_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); @@ -545,8 +544,15 @@ static void riscv_sifive_u_soc_realize(DeviceState *de= v, Error **errp) memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } =20 -static void riscv_sifive_u_machine_init(MachineClass *mc) +static void riscv_sifive_u_machine_instance_init(Object *obj) +{ + +} + +static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); + mc->desc =3D "RISC-V Board compatible with SiFive U SDK"; mc->init =3D riscv_sifive_u_init; mc->max_cpus =3D SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_= COUNT; @@ -554,7 +560,20 @@ static void riscv_sifive_u_machine_init(MachineClass *= mc) mc->default_cpus =3D mc->min_cpus; } =20 -DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) +static const TypeInfo riscv_sifive_u_machine_init_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("sifive_u"), + .parent =3D TYPE_MACHINE, + .class_init =3D riscv_sifive_u_machine_class_init, + .instance_init =3D riscv_sifive_u_machine_instance_init, + .instance_size =3D sizeof(SiFiveUState), +}; + +static void riscv_sifive_u_machine_init_register_types(void) +{ + type_register_static(&riscv_sifive_u_machine_init_typeinfo); +} + +type_init(riscv_sifive_u_machine_init_register_types) =20 static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) { diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 2a08e2a5db..a921079fbe 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -44,12 +44,17 @@ typedef struct SiFiveUSoCState { CadenceGEMState gem; } SiFiveUSoCState; =20 +#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") +#define RISCV_U_MACHINE(obj) \ + OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) + typedef struct SiFiveUState { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent_obj; =20 /*< public >*/ SiFiveUSoCState soc; + void *fdt; int fdt_size; } SiFiveUState; --=20 2.23.0