From nobody Tue Nov 18 09:18:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1609283533; cv=none; d=zohomail.com; s=zohoarc; b=GlbdGb4S8xOA5K8UQycbM2+Iz+yYQLk7kacP1PM/SuOcQvyr6iGej5jKDEg564f1xWwa4FD3+e830b35su+r3lWPxRNgyYoZQJe2P5V9MmNuJ3MCtQXpddT9tsNNvhxGxUM/Yy/LgolAZuU5LeVgV+8eoQhkU4DZgcC4GDnIUHY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1609283533; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=VKrycvbN3vhNaPdXUZ4JEvhlG5GjFpmfJlaaFhV8+do=; b=cSOMf5ffnt3/pRM1PL+33eFjHsA97RKG+LvupHvF/PtPcAqrtF9HLM9m22+3bOy7ycYfXF8f2TbsqggRaDd6vvLN5N3KQBN1GG3nRXTSE8VhQG6aeO+UXUy2h+lEloz6uM0R86px6vW/6+pP68/+TeH6LUs0YLWf2LNSzf4/XPY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160928353371689.38788020389211; Tue, 29 Dec 2020 15:12:13 -0800 (PST) Received: from localhost ([::1]:41234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kuO9z-0001z1-FV for importer@patchew.org; Tue, 29 Dec 2020 18:12:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kuO7s-0008SL-RP for qemu-devel@nongnu.org; Tue, 29 Dec 2020 18:10:01 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]:48957) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kuO7n-0006bh-9P for qemu-devel@nongnu.org; Tue, 29 Dec 2020 18:10:00 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 3327E7470F2; Wed, 30 Dec 2020 00:09:52 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 974527470E0; Wed, 30 Dec 2020 00:09:51 +0100 (CET) Message-Id: <93f3b97f84dbc04f9bb0157b558d728ff4f1a526.1609282253.git.balaton@eik.bme.hu> In-Reply-To: References: Subject: [PATCH 2/7] vt82c686: Rename superio config related parts Date: Tue, 29 Dec 2020 23:50:53 +0100 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable To: qemu-devel@nongnu.org X-Spam-Probability: 8% Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Huacai Chen , f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: BALATON Zoltan From: BALATON Zoltan via Content-Type: text/plain; charset="utf-8" Use less confusing naming for superio config register handling related parts that makes it clearer what belongs to this part. Signed-off-by: BALATON Zoltan --- hw/isa/vt82c686.c | 48 +++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 2633cfe7dc..a6f5a0843d 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -27,7 +27,7 @@ #include "trace.h" =20 typedef struct SuperIOConfig { - uint8_t config[0x100]; + uint8_t regs[0x100]; uint8_t index; uint8_t data; } SuperIOConfig; @@ -35,23 +35,23 @@ typedef struct SuperIOConfig { struct VT82C686BISAState { PCIDevice dev; MemoryRegion superio; - SuperIOConfig superio_conf; + SuperIOConfig superio_cfg; }; =20 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) =20 -static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, - unsigned size) +static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) { - SuperIOConfig *superio_conf =3D opaque; + SuperIOConfig *sc =3D opaque; =20 if (addr =3D=3D 0x3f0) { /* config index register */ - superio_conf->index =3D data & 0xff; + sc->index =3D data & 0xff; } else { bool can_write =3D true; /* 0x3f1, config data register */ - trace_via_superio_write(superio_conf->index, data & 0xff); - switch (superio_conf->index) { + trace_via_superio_write(sc->index, data & 0xff); + switch (sc->index) { case 0x00 ... 0xdf: case 0xe4: case 0xe5: @@ -69,23 +69,23 @@ static void superio_ioport_writeb(void *opaque, hwaddr = addr, uint64_t data, =20 } if (can_write) { - superio_conf->config[superio_conf->index] =3D data & 0xff; + sc->regs[sc->index] =3D data & 0xff; } } } =20 -static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned s= ize) +static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) { - SuperIOConfig *superio_conf =3D opaque; - uint8_t val =3D superio_conf->config[superio_conf->index]; + SuperIOConfig *sc =3D opaque; + uint8_t val =3D sc->regs[sc->index]; =20 - trace_via_superio_read(superio_conf->index, val); + trace_via_superio_read(sc->index, val); return val; } =20 -static const MemoryRegionOps superio_ops =3D { - .read =3D superio_ioport_readb, - .write =3D superio_ioport_writeb, +static const MemoryRegionOps superio_cfg_ops =3D { + .read =3D superio_cfg_read, + .write =3D superio_cfg_write, .endianness =3D DEVICE_NATIVE_ENDIAN, .impl =3D { .min_access_size =3D 1, @@ -112,12 +112,12 @@ static void vt82c686b_isa_reset(DeviceState *dev) pci_conf[0x5f] =3D 0x04; pci_conf[0x77] =3D 0x10; /* GPIO Control 1/2/3/4 */ =20 - s->superio_conf.config[0xe0] =3D 0x3c; - s->superio_conf.config[0xe2] =3D 0x03; - s->superio_conf.config[0xe3] =3D 0xfc; - s->superio_conf.config[0xe6] =3D 0xde; - s->superio_conf.config[0xe7] =3D 0xfe; - s->superio_conf.config[0xe8] =3D 0xbe; + s->superio_cfg.regs[0xe0] =3D 0x3c; /* Device ID */ + s->superio_cfg.regs[0xe2] =3D 0x03; /* Function select */ + s->superio_cfg.regs[0xe3] =3D 0xfc; /* Floppy ctrl base addr */ + s->superio_cfg.regs[0xe6] =3D 0xde; /* Parallel port base addr */ + s->superio_cfg.regs[0xe7] =3D 0xfe; /* Serial port 1 base addr */ + s->superio_cfg.regs[0xe8] =3D 0xbe; /* Serial port 2 base addr */ } =20 /* write config pci function0 registers. PCI-ISA bridge */ @@ -311,8 +311,8 @@ static void vt82c686b_realize(PCIDevice *d, Error **err= p) } } =20 - memory_region_init_io(&s->superio, OBJECT(d), &superio_ops, - &s->superio_conf, "superio", 2); + memory_region_init_io(&s->superio, OBJECT(d), &superio_cfg_ops, + &s->superio_cfg, "superio", 2); memory_region_set_enabled(&s->superio, false); /* * The floppy also uses 0x3f0 and 0x3f1. --=20 2.21.3