From nobody Tue Feb 10 02:44:56 2026 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=oracle.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15503360144781022.9943436528084; Sat, 16 Feb 2019 08:53:34 -0800 (PST) Received: from localhost ([127.0.0.1]:57984 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gv3DO-0003SU-AC for importer@patchew.org; Sat, 16 Feb 2019 11:53:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59011) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gv3C1-0002sO-42 for qemu-devel@nongnu.org; Sat, 16 Feb 2019 11:51:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gv3Bz-0000DM-NG for qemu-devel@nongnu.org; Sat, 16 Feb 2019 11:51:57 -0500 Received: from userp2130.oracle.com ([156.151.31.86]:48010) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gv3By-00005z-NJ for qemu-devel@nongnu.org; Sat, 16 Feb 2019 11:51:55 -0500 Received: from pps.filterd (userp2130.oracle.com [127.0.0.1]) by userp2130.oracle.com (8.16.0.27/8.16.0.27) with SMTP id x1GGiLxj038398; Sat, 16 Feb 2019 16:51:41 GMT Received: from aserv0021.oracle.com (aserv0021.oracle.com [141.146.126.233]) by userp2130.oracle.com with ESMTP id 2qp9xth6n9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 16 Feb 2019 16:51:40 +0000 Received: from aserv0121.oracle.com (aserv0121.oracle.com [141.146.126.235]) by aserv0021.oracle.com (8.14.4/8.14.4) with ESMTP id x1GGpd0S005635 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 16 Feb 2019 16:51:40 GMT Received: from abhmp0022.oracle.com (abhmp0022.oracle.com [141.146.116.28]) by aserv0121.oracle.com (8.14.4/8.13.8) with ESMTP id x1GGpdWH026690; Sat, 16 Feb 2019 16:51:39 GMT Received: from abi.no.oracle.com (/10.172.144.123) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Sat, 16 Feb 2019 08:51:39 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oracle.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=corp-2018-07-02; bh=epiAv/cnTCA34G20Fwj01pgJyaUBKItMIE1Zq5OZhzA=; b=wxfdNEg/AYmlYw8sXnhtuYCXBzZnhpdVpfm19VJpOSJ2nTG/s0Z5+jE4/giydHrUftl+ APu5czR0gJ47CRMPGkRNM1M5mx+PdivHGkfScvjkOS7kjCNINVTk1LjRAen1sxC0yy/y DTJd/8rziLS9I7CDsAOIgK9B3NEMkSd6Q5McIjiWzSvolKqXJU0/OqqY+tgaLc/e8iwp e462s0ku+jOOh0/K245bojVFSJHfugYZqQbqrtCI/zuwj8fQ2qfjnzfTXy+KUXSStleF ubU+RAlzszJC0zUdyg7IAOrmsZIEFgKVbK03Axkq/Kp9oxRjq9ovPre7yd1arnho8LaD Ug== From: Knut Omang To: qemu-devel@nongnu.org Date: Sat, 16 Feb 2019 17:51:11 +0100 Message-Id: <9308ccacc87e29da94aa86c20208459ac2a40024.1550185800.git-series.knut.omang@oracle.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=9169 signatures=668683 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=917 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1902160125 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] X-Received-From: 156.151.31.86 Subject: [Qemu-devel] [PATCH v5 1/2] pcie: Add a simple PCIe ACS (Access Control Services) helper function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S . Tsirkin" , Tal Attaly , Knut Omang , Alex Williamson , Elijah Shakkour , Stefan Hajnoczi Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Implementing an ACS capability on downstream ports and multifunction endpoints indicates isolation and IOMMU visibility to a finer granularity. This creates smaller IOMMU groups in the guest and thus more flexibility in assigning endpoints to guest userspace or an L2 guest. Signed-off-by: Knut Omang --- hw/pci/pcie.c | 39 +++++++++++++++++++++++++++++++++++++++- include/hw/pci/pcie.h | 6 ++++++- include/hw/pci/pcie_regs.h | 4 ++++- 3 files changed, 49 insertions(+) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 230478f..6afc37a 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -906,3 +906,42 @@ void pcie_ats_init(PCIDevice *dev, uint16_t offset) =20 pci_set_word(dev->wmask + dev->exp.ats_cap + PCI_ATS_CTRL, 0x800f); } + +/* ACS (Access Control Services) */ +void pcie_acs_init(PCIDevice *dev, uint16_t offset) +{ + bool is_downstream =3D pci_is_express_downstream_port(dev); + uint16_t cap_bits =3D 0; + + /* For endpoints, only multifunction devs may have an ACS capability: = */ + assert(is_downstream || + (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) || + PCI_FUNC(dev->devfn)); + + pcie_add_capability(dev, PCI_EXT_CAP_ID_ACS, PCI_ACS_VER, offset, + PCI_ACS_SIZEOF); + dev->exp.acs_cap =3D offset; + + if (is_downstream) { + /* Downstream ports must implement SV, TB, RR, CR, and UF (with + * caveats on the latter three that we ignore for simplicity). + * Endpoints may also implement a subset of ACS capabilities, + * but these are optional if the endpoint does not support + * peer-to-peer between functions and thus omitted here. + * Downstream switch ports must also implement DT, while this + * is optional for root ports, so we set that as well: + */ + cap_bits =3D PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | + PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT; + } + + pci_set_word(dev->config + offset + PCI_ACS_CAP, cap_bits); + pci_set_word(dev->wmask + offset + PCI_ACS_CTRL, cap_bits); +} + +void pcie_acs_reset(PCIDevice *dev) +{ + if (dev->exp.acs_cap) { + pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); + } +} diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h index 5b82a0d..e30334d 100644 --- a/include/hw/pci/pcie.h +++ b/include/hw/pci/pcie.h @@ -79,6 +79,9 @@ struct PCIExpressDevice { =20 /* Offset of ATS capability in config space */ uint16_t ats_cap; + + /* ACS */ + uint16_t acs_cap; }; =20 #define COMPAT_PROP_PCP "power_controller_present" @@ -128,6 +131,9 @@ void pcie_add_capability(PCIDevice *dev, uint16_t offset, uint16_t size); void pcie_sync_bridge_lnk(PCIDevice *dev); =20 +void pcie_acs_init(PCIDevice *dev, uint16_t offset); +void pcie_acs_reset(PCIDevice *dev); + void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn); void pcie_dev_ser_num_init(PCIDevice *dev, uint16_t offset, uint64_t ser_n= um); void pcie_ats_init(PCIDevice *dev, uint16_t offset); diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h index ad4e780..1db86b0 100644 --- a/include/hw/pci/pcie_regs.h +++ b/include/hw/pci/pcie_regs.h @@ -175,4 +175,8 @@ typedef enum PCIExpLinkWidth { PCI_ERR_COR_INTERNAL | \ PCI_ERR_COR_HL_OVERFLOW) =20 +/* ACS */ +#define PCI_ACS_VER 0x1 +#define PCI_ACS_SIZEOF 8 + #endif /* QEMU_PCIE_REGS_H */ --=20 git-series 0.9.1