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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=4104b2603=alistair.francis@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/28 18:24:44 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since 4.1. It's not commonly used so let's remove support for it. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- docs/system/deprecated.rst | 20 +-- target/riscv/cpu.h | 1 - target/riscv/cpu.c | 2 - target/riscv/cpu_helper.c | 82 ++++------- target/riscv/csr.c | 138 ++++-------------- .../riscv/insn_trans/trans_privileged.inc.c | 18 +-- target/riscv/monitor.c | 5 - target/riscv/op_helper.c | 17 +-- 8 files changed, 73 insertions(+), 210 deletions(-) diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index a6664bfca9..38865daafc 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -301,16 +301,6 @@ The ``acl_show``, ``acl_reset``, ``acl_policy``, ``acl= _add``, and ``acl_remove`` commands are deprecated with no replacement. Authorization for VNC should be performed using the pluggable QAuthZ objects. =20 -Guest Emulator ISAs -------------------- - -RISC-V ISA privledge specification version 1.09.1 (since 4.1) -''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' - -The RISC-V ISA privledge specification version 1.09.1 has been deprecated. -QEMU supports both the newer version 1.10.0 and the ratified version 1.11.= 0, these -should be used instead of the 1.09.1 version. - System emulator CPUS -------------------- =20 @@ -471,6 +461,16 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfw= d_remove`` (removed in 5.0 The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and 'hostfwd_remove' HMP commands has been replaced by ``netdev_id``. =20 +Guest Emulator ISAs +------------------- + +RISC-V ISA privledge specification version 1.09.1 (removed in 5.1) +'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The RISC-V ISA privledge specification version 1.09.1 has been removed. +QEMU supports both the newer version 1.10.0 and the ratified version 1.11.= 0, these +should be used instead of the 1.09.1 version. + System emulator CPUS -------------------- =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 76b98d7a33..c022539012 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -73,7 +73,6 @@ enum { RISCV_FEATURE_MISA }; =20 -#define PRIV_VERSION_1_09_1 0x00010901 #define PRIV_VERSION_1_10_0 0x00011000 #define PRIV_VERSION_1_11_0 0x00011100 =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 112f2e3a2f..eeb91f8513 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -368,8 +368,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) priv_version =3D PRIV_VERSION_1_11_0; } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { priv_version =3D PRIV_VERSION_1_10_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) { - priv_version =3D PRIV_VERSION_1_09_1; } else { error_setg(errp, "Unsupported privilege spec version '%s'", diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index bc80aa87cf..62fe1ecc8f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -364,57 +364,36 @@ static int get_physical_address(CPURISCVState *env, h= waddr *physical, mxr =3D get_field(env->vsstatus, MSTATUS_MXR); } =20 - if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { - if (first_stage =3D=3D true) { - if (use_background) { - base =3D (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIF= T; - vm =3D get_field(env->vsatp, SATP_MODE); - } else { - base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; - vm =3D get_field(env->satp, SATP_MODE); - } - widened =3D 0; + if (first_stage =3D=3D true) { + if (use_background) { + base =3D (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT; + vm =3D get_field(env->vsatp, SATP_MODE); } else { - base =3D (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; - vm =3D get_field(env->hgatp, HGATP_MODE); - widened =3D 2; - } - sum =3D get_field(env->mstatus, MSTATUS_SUM); - switch (vm) { - case VM_1_10_SV32: - levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; - case VM_1_10_SV39: - levels =3D 3; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_10_SV48: - levels =3D 4; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_10_SV57: - levels =3D 5; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_10_MBARE: - *physical =3D addr; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TRANSLATE_SUCCESS; - default: - g_assert_not_reached(); + base =3D (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + vm =3D get_field(env->satp, SATP_MODE); } - } else { widened =3D 0; - base =3D (hwaddr)(env->sptbr) << PGSHIFT; - sum =3D !get_field(env->mstatus, MSTATUS_PUM); - vm =3D get_field(env->mstatus, MSTATUS_VM); - switch (vm) { - case VM_1_09_SV32: - levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; - case VM_1_09_SV39: - levels =3D 3; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_09_SV48: - levels =3D 4; ptidxbits =3D 9; ptesize =3D 8; break; - case VM_1_09_MBARE: - *physical =3D addr; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TRANSLATE_SUCCESS; - default: - g_assert_not_reached(); - } + } else { + base =3D (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT; + vm =3D get_field(env->hgatp, HGATP_MODE); + widened =3D 2; + } + sum =3D get_field(env->mstatus, MSTATUS_SUM); + switch (vm) { + case VM_1_10_SV32: + levels =3D 2; ptidxbits =3D 10; ptesize =3D 4; break; + case VM_1_10_SV39: + levels =3D 3; ptidxbits =3D 9; ptesize =3D 8; break; + case VM_1_10_SV48: + levels =3D 4; ptidxbits =3D 9; ptesize =3D 8; break; + case VM_1_10_SV57: + levels =3D 5; ptidxbits =3D 9; ptesize =3D 8; break; + case VM_1_10_MBARE: + *physical =3D addr; + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TRANSLATE_SUCCESS; + default: + g_assert_not_reached(); } =20 CPUState *cs =3D env_cpu(env); @@ -588,7 +567,6 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, int page_fault_exceptions; if (first_stage) { page_fault_exceptions =3D - (env->priv_ver >=3D PRIV_VERSION_1_10_0) && get_field(env->satp, SATP_MODE) !=3D VM_1_10_MBARE && !pmp_violation; } else { @@ -941,8 +919,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } =20 s =3D env->mstatus; - s =3D set_field(s, MSTATUS_SPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? - get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->p= riv)); + s =3D set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE)); s =3D set_field(s, MSTATUS_SPP, env->priv); s =3D set_field(s, MSTATUS_SIE, 0); env->mstatus =3D s; @@ -979,8 +956,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) } =20 s =3D env->mstatus; - s =3D set_field(s, MSTATUS_MPIE, env->priv_ver >=3D PRIV_VERSION_1= _10_0 ? - get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->p= riv)); + s =3D set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE)); s =3D set_field(s, MSTATUS_MPP, env->priv); s =3D set_field(s, MSTATUS_MIE, 0); env->mstatus =3D s; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 11d184cd16..383be0a955 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -58,31 +58,11 @@ static int ctr(CPURISCVState *env, int csrno) #if !defined(CONFIG_USER_ONLY) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); - uint32_t ctr_en =3D ~0u; =20 if (!cpu->cfg.ext_counters) { /* The Counters extensions is not enabled */ return -1; } - - /* - * The counters are always enabled at run time on newer priv specs, as= the - * CSR has changed from controlling that the counters can be read to - * controlling that the counters increment. - */ - if (env->priv_ver > PRIV_VERSION_1_09_1) { - return 0; - } - - if (env->priv < PRV_M) { - ctr_en &=3D env->mcounteren; - } - if (env->priv < PRV_S) { - ctr_en &=3D env->scounteren; - } - if (!(ctr_en & (1u << (csrno & 31)))) { - return -1; - } #endif return 0; } @@ -293,9 +273,6 @@ static const target_ulong delegable_excps =3D (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); -static const target_ulong sstatus_v1_9_mask =3D SSTATUS_SIE | SSTATUS_SPIE= | - SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | - SSTATUS_SUM | SSTATUS_SD; static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD; @@ -304,20 +281,11 @@ static const target_ulong hip_writable_mask =3D MIP_V= SSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask =3D MIP_VSSIP; =20 #if defined(TARGET_RISCV32) -static const char valid_vm_1_09[16] =3D { - [VM_1_09_MBARE] =3D 1, - [VM_1_09_SV32] =3D 1, -}; static const char valid_vm_1_10[16] =3D { [VM_1_10_MBARE] =3D 1, [VM_1_10_SV32] =3D 1 }; #elif defined(TARGET_RISCV64) -static const char valid_vm_1_09[16] =3D { - [VM_1_09_MBARE] =3D 1, - [VM_1_09_SV39] =3D 1, - [VM_1_09_SV48] =3D 1, -}; static const char valid_vm_1_10[16] =3D { [VM_1_10_MBARE] =3D 1, [VM_1_10_SV39] =3D 1, @@ -347,8 +315,7 @@ static int read_mstatus(CPURISCVState *env, int csrno, = target_ulong *val) =20 static int validate_vm(CPURISCVState *env, target_ulong vm) { - return (env->priv_ver >=3D PRIV_VERSION_1_10_0) ? - valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; + return valid_vm_1_10[vm & 0xf]; } =20 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) @@ -358,34 +325,21 @@ static int write_mstatus(CPURISCVState *env, int csrn= o, target_ulong val) int dirty; =20 /* flush tlb on mstatus fields that affect VM */ - if (env->priv_ver <=3D PRIV_VERSION_1_09_1) { - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | - MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { - tlb_flush(env_cpu(env)); - } - mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | - MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | - MSTATUS_MPP | MSTATUS_MXR | - (validate_vm(env, get_field(val, MSTATUS_VM)) ? - MSTATUS_VM : 0); + if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | + MSTATUS_MPRV | MSTATUS_SUM)) { + tlb_flush(env_cpu(env)); } - if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { - if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV | - MSTATUS_MPRV | MSTATUS_SUM)) { - tlb_flush(env_cpu(env)); - } - mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | - MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | - MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | - MSTATUS_TW; + mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | + MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | + MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | + MSTATUS_TW; #if defined(TARGET_RISCV64) - /* - * RV32: MPV and MTL are not in mstatus. The current plan is to - * add them to mstatush. For now, we just don't support it. - */ - mask |=3D MSTATUS_MTL | MSTATUS_MPV; + /* + * RV32: MPV and MTL are not in mstatus. The current plan is to + * add them to mstatush. For now, we just don't support it. + */ + mask |=3D MSTATUS_MTL | MSTATUS_MPV; #endif - } =20 mstatus =3D (mstatus & ~mask) | (val & mask); =20 @@ -534,18 +488,12 @@ static int write_mtvec(CPURISCVState *env, int csrno,= target_ulong val) =20 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *va= l) { - if (env->priv_ver < PRIV_VERSION_1_10_0) { - return -1; - } *val =3D env->mcounteren; return 0; } =20 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong va= l) { - if (env->priv_ver < PRIV_VERSION_1_10_0) { - return -1; - } env->mcounteren =3D val; return 0; } @@ -553,8 +501,7 @@ static int write_mcounteren(CPURISCVState *env, int csr= no, target_ulong val) /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v= al) { - if (env->priv_ver > PRIV_VERSION_1_09_1 - && env->priv_ver < PRIV_VERSION_1_11_0) { + if (env->priv_ver < PRIV_VERSION_1_11_0) { return -1; } *val =3D env->mcounteren; @@ -564,32 +511,13 @@ static int read_mscounteren(CPURISCVState *env, int c= srno, target_ulong *val) /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong v= al) { - if (env->priv_ver > PRIV_VERSION_1_09_1 - && env->priv_ver < PRIV_VERSION_1_11_0) { + if (env->priv_ver < PRIV_VERSION_1_11_0) { return -1; } env->mcounteren =3D val; return 0; } =20 -static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *v= al) -{ - if (env->priv_ver > PRIV_VERSION_1_09_1) { - return -1; - } - *val =3D env->scounteren; - return 0; -} - -static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong v= al) -{ - if (env->priv_ver > PRIV_VERSION_1_09_1) { - return -1; - } - env->scounteren =3D val; - return 0; -} - /* Machine Trap Handling */ static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val) { @@ -663,16 +591,14 @@ static int rmw_mip(CPURISCVState *env, int csrno, tar= get_ulong *ret_value, /* Supervisor Trap Setup */ static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val) { - target_ulong mask =3D ((env->priv_ver >=3D PRIV_VERSION_1_10_0) ? - sstatus_v1_10_mask : sstatus_v1_9_mask); + target_ulong mask =3D (sstatus_v1_10_mask); *val =3D env->mstatus & mask; return 0; } =20 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong mask =3D ((env->priv_ver >=3D PRIV_VERSION_1_10_0) ? - sstatus_v1_10_mask : sstatus_v1_9_mask); + target_ulong mask =3D (sstatus_v1_10_mask); target_ulong newval =3D (env->mstatus & ~mask) | (val & mask); return write_mstatus(env, CSR_MSTATUS, newval); } @@ -722,18 +648,12 @@ static int write_stvec(CPURISCVState *env, int csrno,= target_ulong val) =20 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *va= l) { - if (env->priv_ver < PRIV_VERSION_1_10_0) { - return -1; - } *val =3D env->scounteren; return 0; } =20 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong va= l) { - if (env->priv_ver < PRIV_VERSION_1_10_0) { - return -1; - } env->scounteren =3D val; return 0; } @@ -812,15 +732,15 @@ static int read_satp(CPURISCVState *env, int csrno, t= arget_ulong *val) { if (!riscv_feature(env, RISCV_FEATURE_MMU)) { *val =3D 0; - } else if (env->priv_ver >=3D PRIV_VERSION_1_10_0) { - if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { - return -1; - } else { - *val =3D env->satp; - } + return 0; + } + + if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)) { + return -1; } else { - *val =3D env->sptbr; + *val =3D env->satp; } + return 0; } =20 @@ -829,13 +749,7 @@ static int write_satp(CPURISCVState *env, int csrno, t= arget_ulong val) if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return 0; } - if (env->priv_ver <=3D PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) { - tlb_flush(env_cpu(env)); - env->sptbr =3D val & (((target_ulong) - 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); - } - if (env->priv_ver >=3D PRIV_VERSION_1_10_0 && - validate_vm(env, get_field(val, SATP_MODE)) && + if (validate_vm(env, get_field(val, SATP_MODE)) && ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) { if (env->priv =3D=3D PRV_S && get_field(env->mstatus, MSTATUS_TVM)= ) { @@ -1313,8 +1227,6 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_MSTATUSH] =3D { any, read_mstatush, write_mstatush= }, #endif =20 - /* Legacy Counter Setup (priv v1.9.1) */ - [CSR_MUCOUNTEREN] =3D { any, read_mucounteren, write_mucounte= ren }, [CSR_MSCOUNTEREN] =3D { any, read_mscounteren, write_mscounte= ren }, =20 /* Machine Trap Handling */ diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/= insn_trans/trans_privileged.inc.c index 76c2fad71c..5f26e0f5ea 100644 --- a/target/riscv/insn_trans/trans_privileged.inc.c +++ b/target/riscv/insn_trans/trans_privileged.inc.c @@ -85,30 +85,21 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a) static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0) { - gen_helper_tlb_flush(cpu_env); - return true; - } + gen_helper_tlb_flush(cpu_env); + return true; #endif return false; } =20 static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a) { -#ifndef CONFIG_USER_ONLY - if (ctx->priv_ver <=3D PRIV_VERSION_1_09_1) { - gen_helper_tlb_flush(cpu_env); - return true; - } -#endif return false; } =20 static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0 && - has_ext(ctx, RVH)) { + if (has_ext(ctx, RVH)) { /* Hpervisor extensions exist */ /* * if (env->priv =3D=3D PRV_M || @@ -127,8 +118,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sf= ence_vma *a) static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a) { #ifndef CONFIG_USER_ONLY - if (ctx->priv_ver >=3D PRIV_VERSION_1_10_0 && - has_ext(ctx, RVH)) { + if (has_ext(ctx, RVH)) { /* Hpervisor extensions exist */ /* * if (env->priv =3D=3D PRV_M || diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index d725a7a36e..b569f08387 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -215,11 +215,6 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict) return; } =20 - if (env->priv_ver < PRIV_VERSION_1_10_0) { - monitor_printf(mon, "Privileged mode < 1.10 unsupported\n"); - return; - } - if (!(env->satp & SATP_MODE)) { monitor_printf(mon, "No translation or protection\n"); return; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index c6412f680c..b0c49efc4a 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -84,8 +84,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong= cpu_pc_deb) riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); } =20 - if (env->priv_ver >=3D PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >=3D PRV_M)) { + if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >=3D PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } =20 @@ -119,10 +118,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ul= ong cpu_pc_deb) } else { prev_priv =3D get_field(mstatus, MSTATUS_SPP); =20 - mstatus =3D set_field(mstatus, - env->priv_ver >=3D PRIV_VERSION_1_10_0 ? - MSTATUS_SIE : MSTATUS_UIE << prev_priv, - get_field(mstatus, MSTATUS_SPIE)); + mstatus =3D set_field(mstatus, MSTATUS_SIE, + get_field(mstatus, MSTATUS_SPIE)); mstatus =3D set_field(mstatus, MSTATUS_SPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_SPP, PRV_U); env->mstatus =3D mstatus; @@ -147,10 +144,8 @@ target_ulong helper_mret(CPURISCVState *env, target_ul= ong cpu_pc_deb) target_ulong mstatus =3D env->mstatus; target_ulong prev_priv =3D get_field(mstatus, MSTATUS_MPP); target_ulong prev_virt =3D MSTATUS_MPV_ISSET(env); - mstatus =3D set_field(mstatus, - env->priv_ver >=3D PRIV_VERSION_1_10_0 ? - MSTATUS_MIE : MSTATUS_UIE << prev_priv, - get_field(mstatus, MSTATUS_MPIE)); + mstatus =3D set_field(mstatus, MSTATUS_MIE, + get_field(mstatus, MSTATUS_MPIE)); mstatus =3D set_field(mstatus, MSTATUS_MPIE, 1); mstatus =3D set_field(mstatus, MSTATUS_MPP, PRV_U); #ifdef TARGET_RISCV32 @@ -177,7 +172,6 @@ void helper_wfi(CPURISCVState *env) CPUState *cs =3D env_cpu(env); =20 if ((env->priv =3D=3D PRV_S && - env->priv_ver >=3D PRIV_VERSION_1_10_0 && get_field(env->mstatus, MSTATUS_TW)) || riscv_cpu_virt_enabled(env)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); @@ -193,7 +187,6 @@ void helper_tlb_flush(CPURISCVState *env) CPUState *cs =3D env_cpu(env); if (!(env->priv >=3D PRV_S) || (env->priv =3D=3D PRV_S && - env->priv_ver >=3D PRIV_VERSION_1_10_0 && get_field(env->mstatus, MSTATUS_TVM))) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); } else { --=20 2.26.2